Unit 13

Analysis of Clocked Sequential

Circuit By

Ruba A. Salamah241-208 CH91

Fundamentals of Logic Design Chap. 13

This chapter in the book includes:

13.1 A Sequential Parity Checker

13.2 Analysis by Signal Tracing and Timing Charts

13.3 State Tables and Graphs

13.4 General Models for Sequential Circuits

Introduction

Now that we have flip-flops and the concept of memory in our circuit, we might want to determine what a circuit is doing.

The behavior of a clocked sequential circuit is determined from its inputs, outputs and state of the flip-flops (i.e., the output of the flip-flops).

The analysis of a clocked sequential circuit consists of obtaining a table or a diagram of the time sequences of inputs, outputs and states.

E.g., given a current state and current inputs, how will the state and outputs change when the next active clock edge arrives???

Fundamentals of Logic Design Chap. 13

Fundamentals of Logic Design Chap. 13

13.1 A Sequential Parity Checker

8-bit words with odd parity

Fundamentals of Logic Design Chap. 13

A Sequential Parity Checker

Fig 13-1. Block Diagram for Parity Checker

A parity checker for serial data The data enters the circuit sequentially, one bit a time

A Sequential Parity Checker

A parity checker for serial data The data enters the circuit sequentially,

one bit a time

Z = 1 If the total number of 1 inputs received is odd and

no error occured

Z = 0 If the total number of 1 inputs received is even,

an error occurs

Fundamentals of Logic Design Chap. 13

A Sequential Parity Checker

The value of X is read at the time of the active clock edge.

The X input must be synchronized with the clock so that itassumes its next value before the next active clock edge.

The clock input is necessary in order to distinguishconsecutive 0’s or consecutive 1’s on the X input.

Fundamentals of Logic Design Chap. 13

Figure 13-2: Waveforms for Parity Checker

State Graph for Parity Checker

Two states are required

S0

an even number of 1’s received

S1

an odd number of 1’s received

Fundamentals of Logic Design Chap. 13

Figure 13-3: State Graph for Parity Checker (Moore Machine)

Fundamentals of Logic Design Chap. 13

A Sequential Parity Checker

Table 13-1. State Table for Parity Checker

Figure 13-4: Parity Checker

Since the system has two states

we need only one Flip Flop

Fundamentals of Logic Design Chap. 13

13.2 Analysis by Signal Tracing and Timing Charts

1. Assume an initial state of the flip-flops (all flip-flopsreset to 0 unless otherwise specified).

2. For the first input in the given sequence, determinethe circuit output(s) and flip-flop inputs.

3. Determine the new set of flip-flop states after thenext active clock edge.

4. Determine the output(s) that corresponds to thenew states.

5. Repeat 2,3, and 4 for each input in the givensequence.

Basic Procedure

Two Types of Clocked Sequential Circuits

Moore machine the output of a sequential circuits is a function of the present

state only

Mealy machine the output is a function of both the present state and the

input

Moore

Mealy

Fundamentals of Logic Design Chap. 13

State Graphs

Moore Sequential Circuit

As an example of a Moore circuit, we will analyze Figure 13-5 using an input sequence X = 01101. In this circuit, the initial state is A = B = 0, and all state changes occur after the rising edge of the clock, as shown in Figure 13-6.

The X input is synchronized with the clock so that it assumes its next value after each rising edge.

Because Z is a function only of the present state (in this case, Z = A ⊕ B) the output will only change when the state changes.

Fundamentals of Logic Design Chap. 13

Z = A ⊕ B

DA = X ⊕ B’

DB = X + AFundamentals of Logic Design Chap. 13

Fundamentals of Logic Design Chap. 13

Mealy Sequential Circuit

The output depends on both the input (X) and the flip-flops states (A and B), so Z(output) may change either when the input changes or when the flip-flops change state.

Mealy Sequential Circuit

Timing Chart

False Outputs

False OutputsAfter the circuit has changed state and before

the input is changed, the output may temporarily assume an incorrect value.

Also called glitches and spikes

X = 1 0 1 0 1.

A = 0 0 0 1 1 0

B = 0 1 1 1 1 0

Z = 1(0) 1 0(1) 0 1

State Tables and Graphs

In the previous section we analyzed clocked sequential circuits by signal tracing and the construction of timing charts.

Although this is satisfactory for small circuits and short input sequences, the construction of state tables and graphs provides a more systematic approach which is useful for the analysis of larger circuits and which leads to a general synthesis procedure for sequential circuits.

State Tables and Graphs The following method can be used to construct the

transition table:

Example

1. Determine the flip-flop input equations and the output equations from the circuit.

DA = X B’

DB = X + A

Z = A B

Example Continue…2. The next-state equations for the flip-flops are

4. Step 4

Moore State Graph

26

Second Example

Second Example Continue….

1. Determine the flip-flop input equations and the output equations from the circuit.

JA = XB, KA = X

JB = X, KB = XA

Z = XB’+XA+X’A’B

Second Example Continue….

29

Second Example Continue….

Mealy State Graph

Third Example

Serial Adder xi yi ci ci+1 si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Timing Diagram

False output After the circuit has changed state and before the

input is changed, the output may temporarily assume an incorrect value, which we call a false output.

As indicated on the timing chart, this false value arises when the circuit has assumed a new state but the old input associated with the previous state is still present.

The output from a Mealy circuit is only of interest immediately preceding the active clock edge, and extra output changes (false outputs) which might occur between active clock edges should be ignored.

Serial Adder

Initially the carry flip-flop must be cleared

C0=0

Start by adding the least-significant (rightmost) bits in each word.

Reading the sum output just before the rising edge of the clock

State Graph We can use the truth table of the serial adder to

construct the state graph

xi yi ci ci+

1

si

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

State Graph

A Mealy machine Inputs: xi and yi

Output: si

Two states represent a carry (ci) S0 for 0 and S1 for 1

37

Multiple Inputs and Outputs

A state table for a Mealy sequential circuit with two inputs and

two outputs

Multiple Inputs and Outputs

Construction and Interpretation of Timing Charts

Several important points concerning the construction and interpretation of timing charts are summarized as follows:

1. When constructing timing charts, note that a state change can only occur after the rising (or falling) edge of the clock, depending on the type of flip-flop used.

2. The input will normally be stable immediately before and after the active clock edge.

3. For a Moore circuit, the output can change only when the state changes, but for a Mealy circuit, the output can change when the input changes as well as when the state changes.

Construction and Interpretation of Timing Charts

A false output may occur between the time the state changes and the time the input is changed to its new value. (In other words, if the state has changed to its next value, but the old input is still present, the output may be

temporarily incorrect.)

4. False outputs are difficult to determine from the state graph, so use either signal tracing through the circuit or use the state table when constructing timing charts for Mealy circuits.

General Models

A sequential circuit can be divided conveniently into two parts:

Flip-flops

Serve as memory for the circuit

Combinational logic

Realize:

oThe input functions for the flip-flops

oThe output functions

General Model for Mealy Circuit

Example

452004/05/24Analysis of Clocked Sequential Circuits

Minimum Clock Period

General Model for Moore Circuit

State Table X = 0

X1X2 = 00

X = 1 X1X2 = 01

Z = 0 Z1Z2 = 00

Z = 1 Z1Z2 = 01

Homework #3

1. 13.4

2. 13.7

3. 13.13

4. 13.20

5. 13.21

6. 13.27

Solve the following problems from the text book: