Computer Organization  Flip Flops

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Transcript of Computer Organization  Flip Flops
2.3 Build sequential logic circuitCombinational logic circuit Sequential logic circuit Flipflop Build flipflop using logic gates
Objectives:1 Define sequential logic circuit.
2 Differentiate between combinational logic circuit andsequential logic circuit.3 Describe flip  flop.
4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
Sequential & Combinationallogic circuit1 Define sequential logic circuit. 2 Differentiate between combinational logic circuit and sequential logic circuit.
Combinational & Sequential logic circuitCombinational Logic Circuits
Difference between
Basic building blocks include:Sequential Logic Circuits
Basic building blocks include FLIPFLOPS:
Sequentiallogic circuit
S C
Q
R
Q'
Sequential logic is the type of digital systemthat does not only depend on current input, but also the previous history of the system.
For that reason sequential logic requiresmemory elements to function.
The building blocks used to construct devicesthat store data are called flipflops.
Sequential logic circuit
Sequential circuit have loops these enable curcuits to receive feedback
Combinationallogic circuit Combinational logic is an interconnection oflogic gates to generate a specificities logic function where the inputs result in an immediate output, having no memory or storage capabilities.
There are function only based on theirinputs, and NOT based on clocks.
Combinational logic circuit
Combinational circuit is combination of various logic gates
FlipFlop3 Describe flip  flop.
FlipFlop "Flipflop" is the common name given to twostatedevices which offer basic memory for sequential logic operations.
Flipflops are heavily used for digital data storage andtransfer and are commonly used in banks called "registers" for the storage of binary numerical data.
FlipFlop Flipflop are basic storage/memory elements. Flipflop are essentially 1bit storage devices. Types of flipflops are: 1. SR Flipflop 2. JK Flipflop 3. D Flipflop 4. T Flipflop Application of flipflop: 1. Counter 4. Logic controller 2. Register 5. Frequency Divider 3. Memory
SR FlipFlop4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
SR FlipFlop
S
Q
R
Q'
The simplest binary storage device. SR Flipflop have 2 inputs (SET & RESET) and 2outputs (Q & Q).NOTE: Q & Q are compliments of each other
The SR flip flop is sometimes referred to as an SRlatch. The Term latch refers to its use as a temporary memory storage device.
SR FlipFlop Symbol:
SR Flipflop (Active HIGH)
SR Flipflop (Active HIGH)
NOR gate
Symbol
SR FlipFlop Symbol:
SR Flipflop (Active LOW)
SR Flipflop (Active LOW)
NAND gate
Symbol
SR FlipFlop Truth Table:S 0 1 0 1 R 0 0 1 1 Q NC 1 0 0 Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.S RSR Flipflop
Q Q'
(Active HIGH)
S' 1 0 1 0
R' 1 1 0 0
Q NC 1 0 1
Q' NC 0 1 1 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.S RSR Flipflop
Q Q'
(Active LOW)
SR FlipFlop Timing Diagram:
IQ Test!What is the mode of operation of the SR flipflop (set, reset or hold)? What is the output at Q from the SR flipflop (active LOW inputs)?L H
High ?Mode of operation = Set ?
H H
? HighMode of operation = Hold ?
H L
? LowMode of operation = ? Reset
SR FlipFlop4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
Clock
Clock Flipflops: synchronous bistable devices Output changes state at a specified point on atriggering input called the clock.
Change state either at the positive edge (rising edge) orat the negative edge (falling edge) of the clock signal.Clock signalPositive edges Negative edges
SR FlipFlop The Clocked SR Flip Flop like SR flipflop but withextra third input of a standard clock pulse.
Clock
The output of Q and NOT Q will not change(despite making changes to the inputs Set & Reset) in a Clocked RS Flipflop Until receiving a signal from the clock.
Clock SR FlipFlop Symbol:
Clock SR Flipflop (+ve EDGE)
Clock SR Flipflop (+ve EDGE)
Combination gate
Symbol
S CLK Pulse transition detector R CLK' CLK CLK* CLK CLK'
Q
Q'
CLK*
CLKCLK' CLK*
CLKCLK' CLK*
Positivegoing transition
Negativegoing transition
(rising edge)
(falling edge)
Clock SR FlipFlop Truth Table: SR flipflop: on the triggering edge of the clock pulse, S=HIGH and R=LOW is a SET state R=HIGH (and S=LOW) is a RESET state If both SR inputs LOW a NO change
If both SR inputs HIGH a INVALIDTruth table of positive edgetriggered SR flipflop:S 0 0 1 1 R 0 1 0 1 CLK X Q(t+1) Q(t) 0 1 ? Comments No change Reset Set InvalidX = irrelevant (dont care) = clock transition LOW to HIGH
Clock SR FlipFlop Timing Diagram:
How if we add clock as input?Please draw the output waveform for me (Positive edge triggered)
D FlipFlop4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
D FlipFlop Truth Table: D CLK
D C
Q
Q'
D flipflop: single input D (data) D=HIGH a SET state D=LOW a RESET state Q follows D at the clock edge. D flipflop formed by add NOT gate between SR input.S C QD 1 0 CLK Q(t+1) 1 0 Comments Set Reset
R
Q'
= clock transition LOW to HIGH
D FlipFlop Symbol:D CLK Q'
Q
D Flipflop (+ve EDGE)
D Flipflop (+ve EDGE)
Combination gate
Symbol
D FlipFlop Timing Diagram:
CLK
CLK
JK FlipFlop4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
JK FlipFlopsteering NAND gates.
J C K
QQ'
JK flipflop: Q and Q' are feedback to the pulse No invalid state. Include a toggle state. J=HIGH (and K=LOW) a SET state K=HIGH (and J=LOW) a RESET state
If both inputs LOW a NO change If both inputs HIGH a Toggle
JK FlipFlop Symbol:J Q CLK Q' K
JK Flipflop (+ve EDGE)
JK Flipflop (+ve EDGE)
Combination gate
Symbol
JK FlipFlop Truth Table:J 0 0 1 1 K 0 1 0 1 CLK Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle
Q 0 0 0 0 1 1 1 1
J K 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Q(t+1) 0 0 1 1 1 0 1 0
Q(t+1) = J.Q' + K'.Q
JK FlipFlop Timing Diagram:Similar to SR flipflop but toggles when J = K = 1
T FlipFlop4 Identify various types of flipflops. 5 Build SR, JK, T and D flip flop using logic gates. 6 Draw the symbol and truth table of SR, JK, T and D flip flop.
T FlipFlop Truth Table:
TCLK
J C K
Q Q'
T flipflop: singleinput version of the JK flipflop, formed by tying both inputs together.T CLK Q'
Q TQ
Q(t+1) 0 1 1 0
0 0 1 1
0 1 0 1
T 0 1
CLK
Q(t+1) Q(t) Q(t)'
Comments No change Toggle
Q(t+1) = T.Q' + T'.Q
T FlipFlop Symbol:T CLK Q'
Q
T Flipflop (+ve EDGE)
T Flipflop (+ve EDGE)
Combination gate
Symbol
Application: Frequency DivisionHigh J CLK C K CLK CLK Q CLK High J C K QA High J C K QB
T FlipFlop
Q
QAQB
Divide clock frequency by 2.
Divide clock frequency by 4.