2.3 Build sequential logic circuitCombinational logic circuit

Sequential logic circuit

Flip-flop

Build flip-flop using logic gates

Objectives:

• Define sequential logic circuit.

• Differentiate between combinational logic circuit and sequential logic circuit.

• Describe flip - flop.

• Identify various types of flip-flops.

• Build SR, JK, T and D flip – flop using logic gates.

• Draw the symbol and truth table of SR, JK, T and D flip – flop.

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6

Sequential & Combinational

logic circuit

Define sequential logic circuit.

Differentiate between combinational logic circuit and sequential logic circuit.

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2

Difference between Combinational & Sequential logic circuit

2Objective

Basic buildingblocks include:

Basic building blocksinclude FLIP-FLOPS:

Combinational Logic Circuits

Sequential Logic Circuits

Sequentiallogic circuit

• Sequential logic is the type of digital system that does not only depend on current input, but also the previous history of the system.

• For that reason sequential logic requires memory elements to function.

• The building blocks used to construct devices that store data are called flip-flops. 1

Objective

S

C

R

Q

Q'

Sequential circuit have loops – these enable curcuits to receive feedback 1

Objective

Sequential logic circuit

Combinationallogic circuit

• Combinational logic is an interconnection of logic gates to generate a specificities logic function where the inputs result in an immediate output, having no memory or storage capabilities.

• There are function only based on their inputs, and NOT based on clocks.

2Objective

Combinational circuit is combinationof various logic gates

Combinational logic circuit

2Objective

Flip-Flop

Describe flip - flop. 3

Flip-Flop

• "Flip-flop" is the common name given to two-state devices which offer basic memory for sequential logic operations.

• Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data.

3Objective

Flip-Flop

• Flip-flop are basic storage/memory elements.

• Flip-flop are essentially 1-bit storage devices.

• Types of flip-flops are:• 1. SR Flip-flop

• 2. JK Flip-flop

• 3. D Flip-flop

• 4. T Flip-flop

• Application of flip-flop:• 1. Counter 4. Logic controller

• 2. Register 5. Frequency Divider

• 3. Memory

3Objective

SR Flip-Flop

Identify various types of flip-flops.

Build SR, JK, T and D flip – flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flip – flop.

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SRFlip-Flop

• The simplest binary storage device.

• SR Flip-flop have 2 inputs (SET & RESET) and 2 outputs (Q & Q’).

NOTE: Q & Q’ are compliments of each other

• The SR flip flop is sometimes referred to as an SR latch. The Term latch refers to its use as a temporary memory storage device.

4Objective

S

R

Q

Q'

SR Flip-FlopSymbol:

4 5Objective

6SR Flip-flop (Active HIGH)

NOR gateSR Flip-flop (Active HIGH)

Symbol

SR Flip-FlopSymbol:

4 5Objective

6SR Flip-flop (Active LOW)

NAND gateSR Flip-flop (Active LOW)

Symbol

SR Flip-FlopTruth Table:

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6

SR Flip-flop

(Active HIGH)

S R Q Q'

0 0 NC NC No change. Latch remained in present state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

S' R' Q Q'

1 1 NC NC No change. Latchremained in present state.

0 1 1 0 Latch SET.

1 0 0 1 Latch RESET.

0 0 1 1 Invalid condition.

S

R

Q

Q'

S

R

Q

Q'

SR Flip-flop

(Active LOW)

SR Flip-FlopTiming Diagram:

4 5Objective

6

What is the mode of operation of the SR flip-flop (set, reset or hold)?What is the output at Q from the SR flip-flop (active LOW inputs)?

Mode of operation = ?

?H

L

Low

Reset

IQ Test!

Mode of operation = ?

?L

H

Mode of operation = ?

?H

H

High

High

Hold

Set

6Objective

Clock SR Flip-Flop

Identify various types of flip-flops.

Build SR, JK, T and D flip – flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flip – flop.

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6

Clock• Flip-flops: synchronous bistable devices

• Output changes state at a specified point on a triggering input called the clock.

• Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.

Positive edges

Negative edges

Clock signal

ClockSR Flip-Flop

• The Clocked SR Flip Flop like SR flip-flop but with extra third input of a standard clock pulse.

• The output of Q and NOT Q will not change (despite making changes to the inputs Set & Reset) in a Clocked RS Flip-flop Until receiving a signal from the clock.

4Objective

Clock SR Flip-FlopSymbol:

4 5Objective

6Clock SR Flip-flop (+ve EDGE)

Combination gateClock SR Flip-flop (+ve EDGE)

Symbol

4 5Objective

6

SQ

Q'

CLK

Pulse transition detector

R

Positive-going transition

(rising edge)

CLKCLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition

(falling edge)

CLK'

CLK

CLK*

CLKCLK'

CLK*

Clock SR Flip-FlopTruth Table:

• S-R flip-flop: on the triggering edge of the clock pulse,

• S=HIGH and R=LOW is a SET state

• R=HIGH (and S=LOW) is a RESET state

• If both SR inputs LOW a NO change

• If both SR inputs HIGH a INVALID

• Truth table of positive edge-triggered S-R flip-flop:

4 5Objective

6X = irrelevant (“don’t care”)

= clock transition LOW to HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Invalid

Clock SR Flip-FlopTiming Diagram:

4 5Objective

6How if we add clock as input?

Please draw the output waveform for me (Positive edge triggered)

D Flip-Flop

Identify various types of flip-flops.

Build SR, JK, T and D flip – flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flip – flop.

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6

D Flip-FlopTruth Table:

• D flip-flop: single input D (data)

• D=HIGH a SET state

• D=LOW a RESET state

• Q follows D at the clock edge.

• D flip-flop formed by add NOT gate between SR input.

D

CQ

Q'

S

C

R

Q

Q'

CLK

D D CLK Q(t+1) Comments

1 1 Set

0 0 Reset

= clock transition LOW to HIGH

4 5Objective

6

D Flip-FlopSymbol:

4 5Objective

6D Flip-flop (+ve EDGE)

Combination gateD Flip-flop (+ve EDGE)

Symbol

DQ

Q'

CLK

D Flip-FlopTiming Diagram:

4 5Objective

6

CLKCLK

JK Flip-Flop

Identify various types of flip-flops.

Build SR, JK, T and D flip – flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flip – flop.

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5

6

JK Flip-Flop

• J-K flip-flop: Q and Q' are feedback to the pulse-steering NAND gates.

• No invalid state.

• Include a toggle state.• J=HIGH (and K=LOW) a SET state

• K=HIGH (and J=LOW) a RESET state

• If both inputs LOW a NO change

• If both inputs HIGH a Toggle

4 5Objective

6

J

C

K

Q

Q'

JK Flip-FlopSymbol:

4 5Objective

6JK Flip-flop (+ve EDGE)

Combination gateJK Flip-flop (+ve EDGE)

Symbol

J

Q

Q'

CLK

K

JK Flip-FlopTruth Table:

4 5Objective

6

J K CLK Q(t+1) Comments

0 0 Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 Q(t)' Toggle

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Q(t+1) = J.Q' + K'.Q

JK Flip-FlopTiming Diagram:

4 5Objective

6

Similar to S-R flip-flop but toggles when J = K = 1

T Flip-Flop

Identify various types of flip-flops.

Build SR, JK, T and D flip – flop using logic gates.

Draw the symbol and truth table of SR, JK, T and D flip – flop.

4

5

6

T Flip-FlopTruth Table:

• T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.

4 5Objective

6

J

C

K

Q

Q'

CLK

T

TQ

Q'

CLK

T CLK Q(t+1) Comments

0 Q(t) No change

1 Q(t)' Toggle

Q T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Q(t+1) = T.Q' + T'.Q

T Flip-FlopSymbol:

4 5Objective

6T Flip-flop (+ve EDGE)

Combination gateT Flip-flop (+ve EDGE)

Symbol

TQ

Q'

CLK

T Flip-FlopApplication: Frequency Division

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6

J

C

K

Q

CLK

High

CLK

Q

Divide clock frequency by 2.

J

C

K

QA

CLK

High

J

C

K

QB

High

CLK

QA

QB

Divide clock frequency by 4.