1EE241 - Spring 2007Advanced Digital Integrated Circuits

Lecture 23: Latches and Flip-Flops

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Announcements

Final exam on May 8 in classProject presentations on May 3, 1-5pm

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Class MaterialLast lecture

SRAMTodays lecture

Latches and flip-flops

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Latches: ReadingRabaey et al, Chapters 7 and 10Chapter 10 in Chandrakasan et al, by PartoviStojanovic, Oklobdzija, JSSC 4/99

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Latch vs. Flip-Flopz Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Flip-Flop (register)stores data when clock rises

Clk Clk

D D

Q Q

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Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000

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Latch Pair vs. Flip-FlopPerformance metricsDelay metrics

Delay penaltyClock skew penaltyInclusion of logicInherent race immunity

Power/Energy MetricsPower/energyPDP, EDP

Design robustness

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Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

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Latches

D

Clk

Clk

Q

Clk

D

Clk

Q

Transmission-Gate Latch C2MOS Latch

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Latches

Courtesy of IEEE Press, New York. 2000

611

TSPC - True Single Phase Clock Logic

M1

M2

M3

VDD

In

Out

M1

M2

M3

VDD

InOut

M1

M2

M3

VDD

In

Out

M1

M2

M3

VDD

InOut

Precharged N Precharged P Non-precharged N Non-precharged P

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TSPC - True Single Phase Clock Logic

VDD

Out

VDD

VDD

VDD

InStaticLogic

PUN

PDN

Including logic intothe latch

Inserting logic betweenlatches

713

Doubled TSPC Latches

VDD

Out

VDD

Doubled n-TSPC latch

In

VDD

Out

VDD

Doubled p-TSPC latch

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DEC Alpha 21064

Dobberpuhl, JSSC 11/92

815

DEC Alpha 21064

L1: L2:

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DEC Alpha 21064

Integrating logic into latches Reducing effective overhead

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DEC Alpha 21164

L1 Latch L2 Latch

L1 Latch with logic

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Latch Pair as a Flip-Flop

10

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Requirements for the Flip-Flop Design High speed of operation:

Small Clk-Output delay Small setup time Small hold timeInherent race immunity

Low power Small clock load High driving capability Integration of logic into flip-flop Multiplexed or clock scan Robustness Crosstalk insensitivity

- dynamic/high impedance nodes are affected

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Sources of Noise

Courtesy of IEEE Press, New York. 2000

11

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Gate Isolation

Courtesy of IEEE Press, New York. 2000

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Flip-Flop RobustnessRobustness of the storage nodeInput isolationData stored statically, max resistance limitMin capacitance limitPreventing storage node exposure

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Types of Flip-Flops

Latch Pair(Master-Slave)

D

Clk

Q D

Clk

Q

Clk

DataD

Clk

Q

Clk

Data

Pulse-Triggered Latch

L1 L2 L

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Flip-Flop Delay

z Sum of setup time and Clk-output delay is the true measure of the performance with respect to the system speed

z T = TClk-Q + TLogic + Tsetup+ Tskew

D Q

Clk

D Q

Clk

LogicN

TLogicTClk-Q TSetup

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Delay vs. Setup/Hold Times

0

50

100

150

200

250

300

350

-200 -150 -100 -50 0 50 100 150 200

Data-Clk [ps]

Clk

-Out

put [

ps]

Setup Hold

Minimum Data-Output

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Master-Slave Latch Pairs

z Positive setup timesz Two clock phases:

distributed globally generated locally

z Small penalty in delay for incorporating MUX

z Some circuit tricks needed to reduce the overall delay

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Master-Slave Latch Pairs

Case 1: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk

QClk Clkb

Clkb

D

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T-G Master-Slave Latch

Feedback added for static operationUnbuffered inputinput capacitance depends on the phase of the clockover-shoot and under-shoot with long routeswirelength must be restricted at the input

Clock load is highLow powerSmall clk-output delay, but positive setup

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Master-Slave Latches

Case 2: C2MOS

VddVdd Vdd

Vdd

Vdd Vdd

Vdd

VddClk Ck

Ck

Ck

Ck

CkCkb

Ckb

Ckb

CkbQD

Feedback added for static operationLocally generated clockPoor driving capability

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Master-Slave TSPC Flip-flops

VDD

D

VDD

VDD

D

VDD

VDD

D

VDD

D

VDD

VDD

D

VDD

D

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY

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Pulse-Triggered Latches

First stage is a pulse generatorgenerates a pulse (glitch) on a rising edge of the clock

Second stage is a latchcaptures the pulse generated in the first stage

Pulse generation results in a negative setup timeFrequently exhibit a soft edge property

Note: power is always consumed in the pulse generator

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Pulsed Latch

Kozu, ISSCC96

Simple pulsed latch

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Intel/HP Itanium 2

Naffziger, ISSCC02

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Pulse-Triggered Latches

Hybrid Latch Flip-Flop, AMD K-6Partovi, ISSCC96

Vdd

D

Clk

Q

Q

18

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HLFF Operation

1-0 and 0-1 transitions at the input with 0ps setup time

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Hybrid Latch Flip-Flop

Partovi et al, ISSCC96

Skew absorption

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Pulse-Triggered Latches

AMD K-7

Courtesy of IEEE Press, New York. 2000

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Pulse-Triggered LatchesSemi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits98

Clk

D

Vdd Vdd

Q

Q

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transitionLatch has one transistor less in stack - faster than HLFF, but 1-1 glitch existsSmall penalty for adding logic

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Pulse-Triggered Latches

7474, from early 1960s

Clk

D

Q

Q

S

R

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Pulse-Triggered Latches

First stage is a sense amplifier, precharged to high, when Clk = 0After rising edge of the clock sense amplifier generates the pulse on S or RThe pulse is captured in S-R latchCross-coupled NAND has different propagation delays of rising and falling edges

Case 4: Sense-amplifier-based flip-flop, Matsui 1992.DEC Alpha 21264, StrongARM 110

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Sense Amplifier-Based Flip-Flop

Courtesy of IEEE Press, New York. 2000

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Flip-Flop Performance Comparison

Total power consumedinternal powerdata power clock powerMeasured for four casesno activity (0000 and 1111)maximum activity (0101010..)average activity (random sequence)

Test bench

Delay is (minimum D-Q)Clk-Q + setup time

Clk

Data

Clock

50fF

200fF

200fFD Q

Q

Stojanovic, Oklobdzija JSSC 4/99

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Flip-Flop Performance Comparison

0

10

20

30

40

50

60

70

100 150 200 250 300 350 400 450 500

Delay [ps]

Tota

l pow

er [u

W]

mSAFFSDFF

HLFF

C2 MOS

TG M-SOriginal SAFF

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Sampling Window Comparison

Naffziger, JSSC 11/02

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Local Clock Gating

D

QCKI

CKIB

0.85 0.85

2

0.850.5 0.5

0.5

1.2

CP

0.50.85 0.50.85

XNOR

CKIB

CKI

CKIB 0.5

0.5

0.85

0.5

PulseGenerator

Data-TransitionLook-Ahead

DI

Clock on demandFlip-flop

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