L9,10 Flip Flops

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    Basic Sequential Components

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    Flip-Flop (FF)

    Flip-Flop is a memory element used in sequentialcircuit

    FF is an electronic device which has two stable

    states hence it is a bi-stable device.

    FF has two outputs, one is 0 and other is +5 Vdc

    When the FF has its o/p set at 0 Vdc, it can be

    regarded as storing a logic 0 and when its o/p is set

    at +5 Vdc it stores logic 1 FF is capable of serving as one bit of memory

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    Level Triggered

    AFF is said to be level triggered if data present at I/P are

    transferred to O/P only when clock signal reaches its peak

    or lowest Positive level triggered: data transfer takes place when

    clock signal reaches its peak value

    Negative level triggered: data transfer takes place when

    clock signal reaches its lowest value

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    Edge Triggered

    AFF is said to be edge triggered if data present at I/P aretransferred to O/P only at transition in the clock signal

    Positive edge triggered: data transfer takes place at 0-to-1

    transition

    Negative edge triggered: data transfer takes place at 1-to-0 transition

    StateState represents what is stored in memory.

    Previous State:State ofFF before the occurrence of a CLK

    Next State :State ofFF after the occurrence of a CLK

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    SR latch

    The most fundamentallatch is the simple SRlatch, where S and Rstand forsetand reset.

    It can be constructedfrom a pair of cross-coupled NOR (negativeOR) logic gates.

    It is called NOR-Gate

    Latch The stored bit is present

    on the output marked Q

    S R Qn+1 Qn+1

    00

    1

    1

    01

    0

    1

    NC(Qn)0

    1

    RACE

    NC(Qn)1

    0

    RACE

    Reset

    Set

    Logic Diagram

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    When both S and R are 0, the output remains unchanged

    i.e. here next state=previous state

    When S=1, R=0, irrespective of previous condition latch isset to SET state

    Similarly when S=0, R=1,it resets the latch to 0

    when both the S and R are 1, the output of the latch isundefined; here both the outputs will try to reach 0, in otherwords Q=0 and Q=0 at the same time! which violets the

    basic definition of FF that requires Q to be complement ofQ, it leads to RACE condition of the circuit

    the designer has to ensure that S and R inputs are never set to1, if this condition is imposed then the result state is

    unpredictable Doesnt have a clock input

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    SR Latch Using NAND gates :

    S R Qn+1 Qn+1

    0

    0

    1

    1

    0

    1

    0

    1

    RACE

    0

    1

    NC(Qn)

    RACE

    1

    0

    NC(Qn)

    Reset

    Set

    It is also called NAND-

    GATELatch

    The truth table for NAND-gate latch is different from

    that for NOR-gate latch

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    Clocked SRFlip-Flop

    Inputs Outputs

    CLK S R Qn+1 Qn+1

    0

    1

    1

    1

    1

    X

    0

    0

    1

    1

    X

    0

    1

    0

    1

    QnQn0

    1

    RACE

    QnQn1

    0

    RACE

    When CLK level=0 irrespective of S and R inputs, Output

    remains the same When CLK=1, S=0, R=0 Output will not change

    When CLK=1, S=1, R=0 Output is in SET state

    When CLK=1, S=0, R=1 Output is in RESET state

    When CLK=1, S=1, R=1 RACE condition

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    Assignment1:

    Implement cloked SRFF using NAND gates and derive thecorresponding Truth table.

    Solution:

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    Preset and Clear

    When power supply is switched on,the state of circuit is uncertain.Output is set or reset, i.e.unpredictable.

    In some applications user want Q to

    be very specific either SE

    T orRESET.

    Hence we have to consider initialcondition. To accomplish initialcondition we use Preset (direct set)and clear (direct reset) terminal.

    These inputs can be given in 2 ways:

    1) Synchronism with CLK(Synchronous Preset/Clear)

    2)Asynchronism with CLK(Asynchronous Preset/Clear)

    SRFF

    Clear(Cr)

    Preset(Pr)

    CLK

    S

    R

    Q

    Q

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    Inputs Outputs

    Pr Cr CLK S R Qn+1 Qn+1

    X

    0

    01

    1

    1

    1

    1

    X

    0

    10

    1

    1

    1

    1

    0

    1

    11

    1

    1

    1

    1

    X

    X

    XX

    0

    0

    1

    1

    X

    X

    XX

    0

    1

    0

    1

    QnRACE

    01

    Qn0

    1

    RACE

    QnRACE

    11

    Qn1

    0

    RACE

    Truth table of Synchronous Preset and Clear

    SRFF with Preset and Clear

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    Inputs Outputs

    Pr Cr CLK S R Qn+1 Qn+1

    0

    0

    1

    11

    1

    1

    1

    0

    1

    0

    11

    1

    1

    1

    X

    X

    X

    01

    1

    1

    1

    X

    X

    X

    X0

    0

    1

    1

    X

    X

    X

    X0

    1

    0

    1

    RACE

    1

    0

    QnQn0

    1

    RACE

    RACE

    0

    1

    QnQn1

    0

    RACE

    Truth table ofAsynchronous Preset and Clear

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    Unclocked D FF

    To avoid possibility of race condition in SRFF , D flip flopis designed

    An SRFF is converted to a D FF by inserting an inverter

    between S and R and assigning the symbol D to the single

    input.

    Note here that output Q changes as D changes, irrespective

    of previous state.

    Here Qn+1 is simply copy of D input, So functionally D FF

    produces o/p which is equal to input but with some Delay.

    So it is called as delay FF.

    D Input Qn+1 Qn+1

    0

    1

    0

    1

    1

    0

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    Truth table of positive edge triggered D FF

    Input Output

    CLK D Qn+1 Qn+1

    01

    XX

    X

    0

    1

    QnQnQn0

    1

    QnQnQn1

    0

    Edge triggered D FF

    Below is truth table of Positive edge triggered D FF

    When CLK=0 or CLK=1 irrespective of D input, Outputremains the same

    When CLK= i.e. when CLKsignal performs 1-to-0transition, irrespective of D input, Output remains the same

    When CLK= i.e. when CLKsignal performs 0-to-1transition, output Q changes as D changes

    Graphical symbol of

    edge triggered D FF

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    JK flip-flop

    Resolves the problem of undefined outputs associated withSR latch

    It is often used instead of SR latch.

    Logic diagram

    Graphical symbol

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    Inputs Outputs

    CLK J K Qn+1 Qn+1

    0

    1

    X

    X

    X

    0

    0

    1

    1

    X

    X

    X

    0

    1

    0

    1

    QnQ

    nQnQn0

    1

    Qn

    QnQ

    nQnQn1

    0

    Qn

    Truth table of positive edge

    triggered JKFF

    When CLK

    is at HIGH orL

    OW level, both O/Ps remains inprevious state

    When CLKperforms transition from 1-to-0, both O/Ps remains

    in previous state

    When CLKperforms transition from 0-to-1, I/P determines the

    O/P : when J=0, K=0 then state remains unchanged

    when J=0, K=1 then O/P is in Reset state

    when J=1, K=0 then O/P is in Set state

    when J=0, K=1 then O/P is in Toggle state i.e. if Q=1, it

    switches to Q=0 and vice versa

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    T (toggle) flip-flop

    T FF has only one input T

    The T input doesnt specify a value for its output, it specifies

    only whether or not the output should be changed T FF changes its state every clock cycle if its input T is equal

    to 1

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    Truth table of positive edge

    triggered T FF

    Input Output

    CLK T Qn+1 Qn+1

    01

    XX

    X

    0

    1

    QnQnQnQnQn

    QnQnQnQnQn

    When CLK is at HIGH orLOW level, both O/Ps remains inprevious state

    When CLKperforms transition from 1-to-0, both O/Ps remains

    in previous state

    On the rising edge of the clock, if T = 0 then the output of theflip-flop is unchanged; if T=1, the output is inverted i.e. O/P is in

    Toggle state

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    Master Slave JKFF

    Master

    Slave

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    A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a slave.

    Master is positive edge triggered and slave is negative edgetriggered, so when master is active, slave is inactive and viceversa.

    Master responds to its J & K inputs before the slave

    IfJ=1, K=0 master sets on positive clock transition. The higho/p of the master drives the J i/p of the slave, so on the negative

    clock transition, the slave sets. IfJ=0, K=1, master resets on the PT of clock. The high Q

    output of master goes to the K input of slave. So the NT ofclock forces the slave to reset. Again slave has copied themaster.

    IfJ=1, K=1, master toggles on the PT of the clock and the slavethen toggles on the clock NT. Regardless of what the master

    does, slave copies it.

    IfJ=K=0, the FF is disabled and Q remains unchanged.

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    Observations

    Most commonly used flip-flops are D FFs because

    they are useful for temporary storage of data

    Counter circuits can be implemented efficiently by

    using T FFs JKFF combines the behaviours of SR and T FFs

    The JKFF is versatile. It can be used to store data

    just as D FF. It can also be used to build counters, as

    it behaves like T FF ifJ and K input terminals areconnected together.

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    All of the flip-flops and latches shown so far arepositive edge triggered or positive level triggered.

    They also have active high load, set and clearinputs.

    It is possible for those components to be negativeedge triggered or negative level triggered and haveactive low control signals as well.

    Flips-flops and latches can be combined in parallelto store data with more than one bit

    Applications:

    Counter/Timer, register

    Memory element, eliminating keyboard debouncing etc