MotivationAbout lab proto-boards and modules
Must stay in the lab
You are responsible for your assigned equipment for the entire semester.
Today:
Section 6.1.4-6.1.6 of Katz’s Textbook
In-class Activity #1
In-class Activity #2
Truth Table Summary
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Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
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0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
Also called D flip-flop if edge-triggered
NEXT STATE TABLE
D Q Q+
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
Also called T flip-flop if edge-triggered
T Q Q+
Slave section - clock low
Two-stage memory element
Two-phase clock operation - Feedback has no effect until next time clock is high
R
S
Q
Q
Latch
R
S
Q
Q
Latch
Clock
J
K
Q
Q
P
P
Clock
Uses time to break feedback path from outputs to inputs!
Correct Toggle
Effect of Glitches
1's Catching problem:
If input = 1 any time during the clock period (even a 0-1-0 glitch), it will be
interpreted as a 1 for computing output
designer must use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
Built from 3 latches
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Initially Clk = 1
R = S = 0
D changes,
When clock goes high-to-low
R = D’, S = D
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Type When Inputs are Sampled When Outputs are Valid
Un-clocked always propagation delay from
latch input change
latch falling clock edge)
rising clock edge)
falling clock edge)
flipflop (Tsu, Th around falling edge of clock
falling clock edge)
its use is not recommended!
however, fundamental building block for other flipflop types
J-K Flipflop:
but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs
edge-triggered varieties exist
simplest design technique
T Flipflops:
usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
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while the clock is high
Edge triggered device sample inputs on the event
edge
clock is asserted
J K Q Q+
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
J-K NEXT STATE TABLE
Pages 296-298 of Katz
More complex sequential building blocks:
Storage registers, Shift registers, Counters
Available as components in the TTL Catalog
Registers
E.g.: Pentium has several registers
Counters
E.g., the seconds display on a clock.
Both of these have many variations.
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A D F/F is a 1-bit storage register.
A Register File stores a group of words of data.
You specify which word to read or write.
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*
Triangle indicates clock input
When LOAD is false, the F/F doesn’t change.
When LOAD is true during the clock edge, the F/F updates itself.
Sometimes the outputs are 3-state or open collector.
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Stores an 8 bit number
Positive edge triggered
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Stores an 8 bit number
Positive edge triggered
Determines when register contents are visible at the outputs
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74670 4-by-4 Register File with 3-State Outputs
4 words of 4 bits each
Data in: D1,D2,D3,D4 Data out: Q1,Q2,Q3,Q4
Read selects: RB,RA Write selects: WB,WA
Active low read enable /GR, write enable /GW
Can read and write simultaneously.
No clock. Read or write when enables asserted.
Watch out for glitches!
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)
Store several words
Random Access Memories
Same idea as a register file, but optimized for very many words.
Small RAM: 256 4-bit words.
Larger RAM: 4 million 8-bit words.
More details later.
Shift registers shift their bits left or right.
For example, right shift:
We need some way to initialize the shift register.
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Serial input
The shift register doesn’t wrap around from right to left.
Instead, the user provides the new leftmost bit.
Parallel input
Serial output
The bit just shifted off the right is visible at a pin.
Parallel output
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4 modes set by S1,S0
00: hold data (QA,QB,QC,QD)
01: shift right (SR,QA,QB,QC)
10: shift left (QB,QC,QD,SL)
/CLR: asynchronous clear
LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and DSR & DSL for serial inputs.
Note that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits. It's confusing.
Right shift in more detail. All together on the rising clock:
SR QA, QA QB, QB QC, QC QD, QD is lost.
Connecting QD to SR makes a circular shift register.
Left shift in more detail.
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Due: End of Class Today
RETAIN THE LAST PAGES (#3 & #4)!!
For Next Class:
Required Reading:
Sec 7.2, 7.3 of Katz
This reading is necessary for getting points in the Studio Activity!
Q Q
Q Q
Q Q
0 1
1 0
0 0
Q Q
1 1