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Latches and Flip-Flops Discussion D7.1

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Latches and Flip-Flops Latches SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

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Sequential Logic Combinational Logic Output depends only on current input Sequential Logic Output depends not only on current input but also on past input values Need some type of memory to remember the past input values

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Cross-coupled Inverters State 1 State 2

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Latches and Flip-Flops Latches SR Latch D Latch Flip-Flops D Flip-Flop JK Flip-Flop T Flip-Flop

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SR Latch 0 0 1 1 0 1 S' R' Q Q' 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand

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0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand SR Latch S' R' Q Q'

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0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand SR Latch S' R' Q Q'

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0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset SR Latch S' R' Q Q'

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0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 Q 0 ' SR Latch S' R' Q Q'

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0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 Q 0 ' To close or lock with or as if with a latch, To catch or fasten SR Latch S' R' Q Q'

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SR Latch with Enable S' R' Q Q' S R EN S R EN S' R' Q Q' 0 0 1 1 1 Q 0 Q 0 ' Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q 0 Q 0 ' Store

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RS Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

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library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '1' and R = '0' then Q