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Latches and Flip-Flops

Introduction to sequential logic Latches SR Latch

Gated SR Latch

Gated D Latch Flip-Flops

JK Flip-flop

D Flip-flop

T Flip-flop JK Master-Slave Flip-flop

Preset and Clear functions

7474 and 7476 devices

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Flip-Flop

Mostly used sequential circuit blocks for

temporary storage (memory)

For Flip-flops, output changes state only at a

specified triggering input called clock (clk)

For a latch, output changes state at a specified

trigger level (high or low)

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Flip-Flop (cont.)

D Latch vs D Flip Flop

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D

En

Q

Q

D Q

Q

Symbol for clkPositive edge

triggered

Positive level triggered D Latch/

Gated D Latch

Positive edge triggered D Flip-flop

D En Q

Q

0 1 0 1

1 1 1 0

x 0 Q Q

D clk Q Q

0 0 11 1 0

x Q Q

x 0 Q Q

x 1 Q Q

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Flip-Flop (cont.)

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D Q

Q

D

En

Q

Q

D En Q Q

0 0 0 1

1 0 1 0x 1 Q Q

D clk Q Q

0 0 1

1 1 0

x Q Q

x 0 Q Q

x 1 Q Q

Negative level triggered D Latch Negative edge triggered D Flip-flop

Negative edgetriggered

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Flip-flop (cont.)

Draw the output waveform for the positive

and negative edge triggered D flip-flops

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clk

D

Q (+ve Flip-flop)

Q (-ve Flip-flop)

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Flip-Flop (cont.)

How to design flip-flops?

Recall the Gated D Latch

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DQ

Q

En

For Gated D Latch,

Q

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Flip-Flop (cont.)

Pulse transition detector

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clk

pulse

clk

pulse

PTDclk pulse

Pulse transition detector

Circuit diagram

Waveform

Block diagram

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D Flip-flop

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A positive edge of clk results in a short pulse at output of PTD,therefore, causes Q

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SR Flip-flop

Recall the problem with SR Flip-flop

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SQ

Q

clk PTD

R

When S = 1 and R = 1, the outputs are invalid (both Q and Q equal to 1)

To overcome this problem, Q and Q is fed back to the Gated NANDs

which now becomes the JK Flip-flop

Sx and Rx can never be equal to 0 at same time

Sx

Rx

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JK Flip-flop

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JQ

Q

clk PTD

K

J K clk Q Q

0 0 Q Q

0 1 0 1

1 0 1 0

1 1 Q Q

x x - Q Q

When J = 1 and K = 1, Q and Q toggles

When J = 0 and K = 0, Q and Q maintains

When J = 0 and K = 1, Q = 0 (Reset)

When J = 1 and K = 0, Q = 1 (Set)

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D Flip-flop

We can also construct a D Flip-flop from JKFlip-flop by shorting J and K with an inverter

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DQ

Q

clk PTD

Q

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T Flip-flop

Another type of flip-flop, the T Flip-flop can beconstructed from the JK flip flop by shorting J

and K inputs

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T Q

Q

clk PTD

Q

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T Flip-flop (cont.)

Draw the output waveform for the positive

edge triggered T Flip-flop

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clk

T

Q

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JK Master Slave Flip-Flop

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J

K

Q

Q

J

K

Q

Q

Master Slave

Master latches data at positive edge of clk

Slave latches data at negative edge of clk

Qms is therefore valid on the negative edge of clk

Jms

Kms

Qms

Qms

Qn

Qn

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JK Master Slave Flip-flop (cont.)

Draw the output for JK Flip-flop and the JK

Master Slave Flip-flop (MS-JK)

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clk

J

K

Q (JK Flip-flop)

Q (MS-JK Flip-flop)

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Flip-flop Extra Features

Positive edge triggered D Flip-flop with activehigh Input Enable

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S

F

D0

D1 D Q

Q

En

D Q

Q

clk

D Q

Q

En

If En = 1

Q

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Flip-flop Extra Features (cont.)

Positive Edge Triggered D Flip-flop with activelow clear and active low preset functions

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S1

F

D2

D3

S0

D0

D1

CLR PRE

CLR PRE clk Q Q

0 0 x 1 1

0 1 x 0 1

1 0 x 1 0

1 1 D DCLR PRE

S1

F

D2

D3

S0

D0

D1

10

1

0

1

1

Q

Q

D D Q

QclkD Q

Q

PRE

CLR

The D Flip-flop

only functionswhen CLR = 1

and PRE = 1

4x1 Mux

4x1 Mux

When 0, Q

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Flip-flop Extra Features (cont.)

Putting all together Positive Edge TriggeredD Flip-flop with active high enable, active low

preset and active low clear

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D Q

Q

PRE

CLREn

What is the input condition that Q

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Flip-flop IC

The 7474 Dual Positive Edge Triggered D Flip-flop with preset, clear, and complementary

outputs

The 7476 Dual Master-Slave JK Flip-flops withclear, preset and complementary outputs

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