EE365 Adv. Digital Circuit Design Clarkson University Lecture #10 Latches, Flip Flops & Sequential...

EE365Adv. Digital Circuit Design

Clarkson University

Lecture #10

Latches, Flip Flops & Sequential PALS

Topics

• Basic Definitions

• Latches

• Edge-Triggered Flip-Flops

• Timing Requirements

Rissacher EE365Lect #10

Sequential Circuits

• Output depends on current input and past history of inputs.

• “State” embodies all the information about the past needed to predict current output based on current input.– State variables, one or more bits of

information.


Describing Sequential Circuits

• State table– For each current-state,

specify next-states as function of inputs

– For each current-state, specify outputs as function of inputs


Describing Sequential Circuits

• State diagram– Graphical version of state table


Clock signals

• Very important with most sequential circuits– State variables change state at clock edge.


Bistable element• The simplest sequential circuit

• Two states– One state variable, say, Q

HIGH LOW

LOW HIGH


Bistable element• The simplest sequential circuit

• Two states– One state variable, say, Q

LOW HIGH

HIGH LOW


Analog analysis• Assume pure CMOS thresholds, 5V rail

• Theoretical threshold center is 2.5 V


Analog analysis

• Assume pure CMOS thresholds, 5V rail

• Theoretical threshold center is 2.5 V2.5 V 2.5 V

2.5 V 2.5 V


Analog analysis

• Assume pure CMOS thresholds, 5V rail

• Theoretical threshold center is 2.5 V

2.5 V

2.5 V 2.5 V

2.0 V

2.0 V 4.8 V

2.5 V2.51 V4.8 V 0.0 V

0.0 V 5.0 V


Metastability

• Metastability is inherent in any bistable circuit

• Two stable points, one metastable point


Another look at metastability


“sube y baja” behavior


Why all the harping on metastability?

• All real systems are subject to it– Problems are caused by “asynchronous inputs” that

do not meet flip-flop setup and hold times.– Details in Chapter-7 flip-flop descriptions and in

Section 8.9– Especially severe in high-speed systems– since clock periods are so short, “metastability

resolution time” can be longer than one clock period.

• Many digital designers, products, and companies have been burned by this phenomenom.


Back to the bistable….

• How to control it?– Screwdriver– Control inputs

• S-R latch


S-R latch operation

Metastability is possibleif S and R are negatedsimultaneously.

(try it in Foundation)


S-R latch timing parameters

• Propagation delay

• Minimum pulse width


S-R latch symbols


S-R latch using NAND gates


S-R latch with enable


D latch


D-latch operation


D-latch timing parameters• Propagation delay (from C or D)

• Setup time (D before C edge)

• Hold time (D after C edge)


Edge-triggered D flip-flop behavior


D flip-flop timing parameters• Propagation delay (from CLK)

• Setup time (D before CLK)

• Hold time (D after CLK)


TTL edge-triggered D circuit• Preset and

clear inputs– like S-R

latch

• 3 feedback loops– interesting

analysis

• Light loading on D and C


CMOS edge-triggered D circuit• Two feedback loops (master and slave latches)• Uses transmission gates in feedback loops• Interesting analysis method (Sec. 7.9)


Other D flip-flop variations

• Negative-edge triggered

• Clock enable

• Scan


Scan flip-flops -- for testing

• TE = 0 ==> normal operation• TE = 1 ==> test operation

– All of the flip-flops are hooked together in a daisy chain from external test input TI.

– Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO.


J-K flip-flops

• Not used much anymore


T flip-flops

• Important for counters


In Class Practice Problem

The characteristic Equation for a D latch is:

Q* = D

Write the Characteristic Equation for an S-R latch


In Class Practice Problem

The characteristic Equation for an S-R latch is:

Q* = S + R’ • Q


In Class Practice Problem #2

Write characteristic equations for each of the following:

• J-K flip flop• T flip flop• T flip flop with enable




J-K flip flop:

T flip flop:


Write characteristic equations for each of the following:

• J-K flip flop– Q* = J • Q’ + K’ • Q

• T flip flop– Q* = Q’

• T flip flop with enable– Q* = EN • Q’ + EN’ • Q


• SSI LATCHES and Flip-Flops


Sequential PALs

• 16R8


One output of 16R8

• 8 product terms to D input of flip-flop– positive edge triggered, common clock for all

• Q output is fed back into AND array– needed for state machines and other applications

• Common 3-state enable for all output pins


PAL16R6

• Six registered outputs

• Two combinational outputs (like the 16L8’s)


GAL16V8

• Each output is programmable as combinational or registered

• Also has programmable output polarity


GAL16V8 output logic macrocell


GAL22V10

• More inputs

• More product terms

• More flexibility


GAL22V10 output logic macrocell


Next time

• State Machine Types

• State machine Design


EE365 Adv. Digital Circuit Design Clarkson University Lecture #10 Latches, Flip Flops & Sequential...

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