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Latches and Flip-Flops
Discussion D7.1
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
Sequential Logic
• Combinational Logic– Output depends only on current input
• Sequential Logic– Output depends not only on current input but
also on past input values– Need some type of memory to remember the
past input values
Cross-coupled Inverters
0
1
1
0
State 1 State 2
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
SR Latch
0 00 11 01 1
S' R' Q Q'1
1
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
S’
R’
Q
Q’
Q
0 00 11 01 1
0
1
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
0
1
1
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
0
1
1
0 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
1
1
0 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
0
1
0 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
0
1
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
0
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
1
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
0
0
1
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
1 1 Disallowed
Q0 Q0'
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
0 00 11 01 1
1
1
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
1 1 Disallowed
Q0 Q0'
To close or lock with or as if with a latch, To catch or fasten
S’
R’
Q
Q’
Q
SR Latch
S' R' Q Q'
SR Latch with EnableS'
R'
Q
Q'
S
R
EN
S R EN S' R' Q Q'
0 0 1 1 1 Q0 Q0' Store 0 1 1 1 0 0 1 Reset1 0 1 0 1 1 0 Set1 1 1 0 0 1 1 DisallowedX X 0 1 1 Q0 Q0' Store
RS Latch
RS Latch
R
S
Q
Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.
Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.
Assertions can be active HIGH or active LOW
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity rslatch is port(
R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC
);end rslatch;
architecture rslatch of rslatch isbegin
process(R,S)begin if S = '1' and R = '0' then
Q <= '1'; elsif S = '0' and R = '1' then
Q <= '0'; end if;end process;
end rslatch;
RS Latch
R
S
Q
Active HIGH
RS Latch -- Active High
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity rslatch is port(
R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC
);end rslatch;
architecture rslatch of rslatch isbegin
process(R,S)begin if S = '0' and R = '1' then
Q <= '1'; elsif S = '1' and R = '0' then
Q <= '0'; end if;end process;
end rslatch;
RS Latch
R
S
Q
Active LOW
RS Latch -- Active Low
How can you make this RS latch from gates?
RS Latch
R
S
Q
Q is set to 1 when S is asserted, and remains unchanged when S is disasserted.
Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted.
Assertions can be active HIGH or active LOW
R S Q Q0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 01 1 1 1
RS LatchR
S
Q
Q is set to 1 when S is asserted (1), and remains unchanged when S is disasserted (0).
Q is reset to 0 when R is asserted (1), and remains unchanged when R is disasserted (0).
RSQ
00 01 11 10
0
1
Q = R'Q + R'S + SQ
1 1
1
1store
set
reset
store
Q
S
R
R S Q Q0 0 0 00 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 01 1 1 1
store
set
reset
store
RS LatchR
S
Q
RS Latch
Q = R'Q + R'S + SQ
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity rslatchgates is port(
R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC
);end rslatchgates;
architecture rslatchgates of rslatchgates is signal Q1: std_logic;
begin
Q1 <= (not R and Q1) or (not R and S) or (S and Q1); Q <= Q1;
end rslatchgates;
Q
S
RQ1
Q
S
R
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
D Latch
D Latch
D
EN
Q
Q follows D when EN is high, and remains unchanged when EN is low..
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity dlatch is port(
D : in STD_LOGIC; EN : in STD_LOGIC; Q : out STD_LOGIC
);end dlatch;
architecture dlatch of dlatch isbegin
process(D,EN)begin if EN = '1' then
Q <= D; end if;end process;
end dlatch;
D Latch
D
EN
Q
D Latch
D Latch
Q
Q'
EN
D S'
R'
S
R S R EN Q Q'
0 0 1 Q0 Q0' Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0' Store
0 1 0 11 1 1 0X 0 Q0 Q0'
D EN Q Q'
D Latch
0 1 0 11 1 1 0X 0 Q0 Q0'
D EN Q Q' Note that Q follows Dwhen EN in high,and is latched when EN goes to zero.
Q
Q'
EN
D S'
R'
S
R
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
D Flip-Flop
0 0 11 1 0X 0 Q0 Q0'
D clk Q Q'
D gets latched to Q on the rising edge of the clock.
Positive edge triggered
if rising_edge(clk) then Q <= D;end if;
Behavior
clk
D Q
Q'
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity dflipflop is port(
D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC
);end dflipflop;
architecture dflipflop of dflipflop issignal QS: STD_LOGIC;begin
process(D,clk)begin if rising_edge(clk) then
QS <= D; end if;end process;Q <= QS;NotQ <= not QS;
end dflipflop;
clk
D Q
Q'
D Flip-Flop
library IEEE;use IEEE.STD_LOGIC_1164.all;
entity dflipflop is port(
D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC
);end dflipflop;
architecture dflipflop of dflipflop issignal QS: STD_LOGIC;begin
process(D,clk)begin if clk'event and clk = '1' then
QS <= D; end if;end process;Q <= QS;NotQ <= not QS;
end dflipflop;
clk
D Q
Q'
D Flip-Flop
Master Slave
D D
EN EN
clk
QMQD
Master-Slave D Flip-Flop
Master-Slave D Flip-Flop
Master Slave
D D
EN EN
clk
QMQD
Recall the SR Latch
0 00 11 01 1
0
0
1
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
1 1 Disallowed
Q0 Q0'
S’
R’
Q
Q’
Q S' R' Q Q'
Edge-triggered D Flip-flop
0 1
1
1 0
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
1
0
1 0
1
1 0
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
1
0
1 0
1
0 1
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
1
0
0 1
1
0 1
0
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
1 1
0
0 1
0
0
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
1 1
0
1 1
0
0
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Edge-triggered D Flip-flop
0 1
1
1 0
1
0
1
S’
R’
Q
Q’
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
Spartan 3 CLB slices
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
J-K Flip-flops
Qnext = JQ' + K'Q
J K Qnext
0 0 Q0 1 01 0 11 1 Q'
CLK
D Q
Q’
J
K
CLK
Q
Q’
J-K Flip-flopsJ K Qnext
0 0 Q0 1 01 0 11 1 Q'
J
CLK
Q
Q’K
0 0 Q0 Q’00 1 0 11 0 1 01 1 TOGGLEX X 0 Q0 Q’0
J K CLK Q Q’
Latches and Flip-Flops
• Latches– SR Latch– D Latch
• Flip-Flops– D Flip-Flop– JK Flip-Flop– T Flip-Flop
T Flip-flops
CLK
D Q
Q’
CLK
Q
Q’T
nextQ T Q T Qnext
0 Q1 Q'
T Flip-flops
T Qnext
0 Q1 Q'
T
CLK
Q
Q’
0 Q Q’ 1 Q’ Q
T CLK Q Q’
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