Flip Flops Latch

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10/26/22 10/26/22 1 CHAPTER OUTLINE ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICES NAND Gate Latch NOR Gate Latch Troubleshooting Case Study Clock Signals and Clocked Flip-Flops Clocked S-C Flip-Flop Clocked J-K Flip-Flop Clocked D Flip-Flop D Latch (Transparent Latch) Asynchronous Inputs IEEE/ANSI Symbols Flip-Flop Timing Considerations Potential Timing Problem in FF Circuits Master/Slave Flip-Flops Flip-Flop Applications Flip-Flop synchronization Detecting an Input Sequence Data Storage and Transfer Serial Data Transfer: Shift Registers Frequency Division and Counting Microcomputer Application Schmitt-Trigger Devices One-Shoot (Mono stable Multivibrator) Analyzing Sequential Circuits Clock Generator

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Flip Flops Latch

Transcript of Flip Flops Latch

  • CHAPTER OUTLINEECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESNAND Gate LatchNOR Gate LatchTroubleshooting Case StudyClock Signals and Clocked Flip-FlopsClocked S-C Flip-FlopClocked J-K Flip-FlopClocked D Flip-FlopD Latch (Transparent Latch)Asynchronous InputsIEEE/ANSI SymbolsFlip-Flop Timing ConsiderationsPotential Timing Problem in FF CircuitsMaster/Slave Flip-FlopsFlip-Flop ApplicationsFlip-Flop synchronizationDetecting an Input SequenceData Storage and TransferSerial Data Transfer: Shift RegistersFrequency Division and CountingMicrocomputer ApplicationSchmitt-Trigger DevicesOne-Shoot (Mono stable Multivibrator)Analyzing Sequential CircuitsClock Generator CircuitsTroubleshooting Flip-Flop Circuits

  • OBJECTIVES (SELECTED TOPICS)ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESAt the end of the session, student should be able toConstruct and analyze the operation of a latch flip-flop made from NAND or NOR gates.Debounce a mechanical switch by using a latch circuit.Identity several types of edge-triggered flip-flops, such as the J-K, D-type, and S-C.

  • GENERAL DIGITAL SYSTEM DIAGRAMECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESCOMBINATIONAL LOGIC GATESMEMORY ELEMENTSCOMBINATIONALOUTPUTSMEMORYOUTPUTSEXTERNAL INPUTS

  • GENERAL FLIP-FLOP SYMBOL ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESFFINPUTSQNORMAL OUTPUTINVERTED OUTPUTCALLED HIGH OR 1; ALSO CALLED SET STATE CALLED LOW OR 0; ALSO CALLED CLEAR/RESET STATE

  • NOR GATE LATCHECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESCLICK ICON TO SIMULATE!SETCLEARSC00100111QNo ChangeQ=1Q=0InvalidQSCNormallyLowQNAND GATE LATCHNormallyHigh

  • EXAMPLE 5-1ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESThe waveforms below are applied to the inputs of the NAND Gate Latch. Assume that initially Q = 0, and determine the Q waveform.

  • EXAMPLE 5-3ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESAssume that Q=0 initially, and determine the Q waveform for the NOR latch inputs.

  • EXAMPLE 5-2ECE 416: CHAPTER 5 FLIP-FLOP AND RELATED DEVICESIt is virtually impossible to obtain a "clean" voltage transition from a mechanical switch, because of the phenomenon of contact bounce. This is illustrated in below, where the action of moving the switch from contact position 1 to 2 produces several output voltage transitions as the switch bounces (makes and breaks contact with contact 2 several times) before coming to rest on contact 2.

  • EXAMPLE 5-2

  • TROUBLESHOOTING CASE STUDYAnalyze and describe the operation of the circuit.CLICK ICON TO SIMULATE!

  • CLOCK SIGNALS

  • CLOCKED FLIP-FLOPSClocked FFs have a clock input (CLK) that is active on either (a) the PGT or (b) the NGT. The control inputs determine the effect of the active clock transition

  • SETUP AND HOLD TIMESControl Inputs must be held stable for (a) a time ts prior to active clock transition and (b) a time tH after the active block transition

  • CLOCKED S-C FLIP-FLOP(a) Clocked S-C FF that responds only to the positive-going edge of a clock pulse; (b) truth table; (c) typical waveforms

  • CLOCKED S-C FLIP-FLOPClocked S-C FF that triggers only on negative-going transitions

  • INTERNAL CIRCUITRY OF THE EDGE TRIGGERED S-C FLIP-FLOPSimplified version of the internal circuitry for an edge triggered S-C flip-flop

  • INTERNAL CIRCUITRY OF THE EDGE TRIGGERED S-C FLIP-FLOPImplementation of edge-detector circuits used in edge-triggered flip-flops: (a) PGT; (b) NGT. The duration of the CLK pulses is typically 2-5 nanoseconds

  • CLOCKED J-K FLIP-FLOP(a) Clocked J-K FF that responds only to the positive-going edge of a clock pulse; (b) truth table; (c) typical waveforms

  • CLOCKED J-K FLIP-FLOPClocked J-K FF that triggers only on negative-going transitions

  • INTERNAL CIRCUITRY OF THE EDGE TRIGGERED J-K FLIP-FLOPInternal circuitry for an edge triggered J-K flip-flop

  • CLOCKED D FLIP-FLOP(a) Clocked D FF that responds only to the positive-going edge of a clock pulse; (b) truth table; (c) typical waveforms

  • IMPLEMENTATION OF THE D FF FROM AN SC FF

  • IMPLEMENTATION OF THE D FF FROM AN JK FF

  • PARALLEL DATA TRANSFERParallel trasfer of binary data using D FF

  • D LATCH (TRANSPARENT LATCH)D latch: (a) structure (b) truth table (c) logic symbol

  • IMPLEMENTATION OF THE D FF FROM AN SC FF

  • IMPLEMENTATION OF THE D FF FROM AN JK FF

  • PARALLEL DATA TRANSFERParallel trasfer of binary data using D FF