Sequential Circuits & Sequential Circuits & Flip-FlopsFlip-Flops

Sequential Circuits & Sequential Circuits & Flip-FlopsFlip-Flops

•Basic LatchBasic Latch•Gated SR & D LatchesGated SR & D Latches

•D, T & JK Flip-FlopsD, T & JK Flip-Flops•MetastabilityMetastability

Objectives• Upon completion of this chapter, student

should be able to:– Describe the operation and use of latch and flip-

flops (S R, D, J K)– Draw the flip-flops logic symbol.– Draw timing diagram based on flip-flop operation.– Recognize the difference between a latch and a flip-

flop.– Understand the flip-flops operating characteristics– Apply flip-flops in basic applications.

Summary of previous week

• Decoder• 7 segment display• Encoder• Multiplexer• Demultiplexer

Function

Truth table

Sequential Circuits• Combinational – output depends only on the input.

– Do not have memory– Cannot store state

• Sequential – output depends on input and past behavior.– Require use of storage elements.– Contents of storage elements is called state.– Circuit goes through sequence of states as a result of

changes in inputs.

Sequential Circuits Types

• Synchronous– State changes

synchronized by one or more clocks

– Easier to analyze because can factor out gate delays

– Set clock so changes allowed to occur before next clock pulse

• Asynchronous– Changes occur

independently– Potentially faster– Harder to analyze

Simple Memory Elements

• A simple memory element: feedback will hold value

• A memory element with NOR gates: Use Set/Reset to change stored value

A B

Reset

Set Q

SR Latch• Basic storage made from gates• Rearrangement of memory element from previous slide!

QR

SQ

Function Table

S R Q Function

0 0 Qo Hold

0 1 0 Reset

1 0 1 Set

1 1 ? Not allowed

S Q

Q R

Graphical symbol

• If S & R both 1 at same time, Q = Q’ = 1

SR LatchDetailed

Function Table

S R Q Q+

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

0

1

SR0X

10

X0

01

State Transition Diagram:

The excitation table in graphical form

Excitation Table

Q Q+ S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Excitation Table: What are the necessary inputs to cause a particular kind of change in state?

Latch• Similar – made from

NANDs

RS

Function Table

S R Q Function

1 1 Qo Hold

1 0 0 Reset

0 1 1 Set

0 0 ? Not allowed

Gated SR Latch• Add Control Input

– Typically, control signal is referred to as a clock

• Clock controls when state can change

EN

EN

Gated SR Latch

R

C

Q

Q

S

1

0

1

0

1

0

1

0

1

0

Time

?

?

S Q

Q

C

R

Graphical symbol

EN

EN

Gated D Latch• No illegal state

Q

S

R

D (Data)

(a) Circuit

Q

EN

EN

Gated D Latch

t 1 t 2 t 3 t 4

Time

D

Q

(d) Timing diagram

D Q

Q

(c) Graphical symbol

C EN

EN

D Latch

Detailed Function

Table

D Q Q+

0 0 0

0 1 0

1 0 1

1 1 1

Excitation Table

Q Q+ D

0 0 0

0 1 1

1 0 0

1 1 1

0

1

0

1

1

0

State Transition Diagram

Standard Symbols – Latches

Circle at input indicates negation

ENEN

Flip-Flops• Ensure only one transition• Two major types• Master-Slave

– Two stage– Output not changed until clock disabled

• Edge triggered– Change happens when clock level

changes

Edge-Triggered Flip-Flops

• Synchronous input– Change state either at positive edge or

negative edge of a clock pulse.

• Edge triggered S-R flip flop

S-R Flip-Flop

S-R Flip-Flop• Edge-triggering-

pulse transition detector, produces a very short-duration spike during the transition of the clock pulse.

Symbols – Edge-Triggered

Arrow indicates edge trigger

A positive-edge-triggered D flip-flop

D

Clock

P4

P3

P1

P2

5

6

1

2

3

(a) Circuit

D Q

Q

(b) Graphical symbol

Clock

Q

Q

4

D Flip-Flop

D Flip-Flop

Comparison of level-sensitive and edge-triggered devices

D Q

Q

D Q

Q

D Q

Q

D

Clock Q a

Q b

Q c

Q c

Q b

Q a

(a) Circuit

Clk D

Clock

Q a

Q b

(b) Timing diagram

Q c

D Latch versus D Flip-Flop

EN

JK Flip-Flop

(a) Circuit

J Q

Q

(b) Truth table (c) Graphical symbol

K

K

01

Q t 1+ Q t 0

J

00

0 11

1 Q t 1

JK Flip-Flop

(b) Timing Diagram

JK Flip-Flop

Detailed Function

Table

J K Q Q+

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Excitation Table

Q Q+

J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

0

1

SR0X

1X

X0

X1

State Transition Diagram

Asynchronous Inputs• State of the flip flop change independent

of the clock.

Flip-flops Operating Characteristics

• Propagation delay time– tPLH from triggering edge of clock to LOW-to-

HIGH output transition.– tPHL from triggering edge of clock pulse to

HIGH-to-LOW output transition.– tPLH from leading edge of preset input to

LOW-to-HIGH output transition.– tPHL from leading edge of clear input to

HIGH-to-LOW ouput transition.

Flip-flops Operating Characteristics

• Set-up time,ts– Minimum interval required for the logic level to be

maintained constantly on the inputs prior to the triggering edge of clock pulse.

• Hold-time, th– Minimum interval required for the logic levls to remain on

the inputs after the triggering edge of the clock pulse.• Maximum clock frequency response

– Highest rate at which a flip-flop can be reliably triggered• Pulse width, tw

– Minimum pulse widths for reliable operation.• Power dissipation

– Total power consumption of the device.– P=VCC X ICC

Flip-flops Applications• Parallel data storage

Flip-flops Applications• Frequency division

Flip-flops Applications• Counting

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