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Storage elements

Introduction to Sequential Circuits

The state of storage element (flip-flop) is switched by a gate signal (C) state transitions.

C

nQ 1nQ +Positive-edge response

Negative-edge response

Master-Slave Flip-Flops

Negative-edge Triggered Flip-Flops

Positive-edge Triggered Flip-Flops

Flip-Flops

"Pulse-triggered" flip-flop

C

nQ 1nQ +

"Positive-edge-triggered" flip-flop

C

nQ 1nQ +

1

Clock/Gate signal in symbol

C,CLK C,CLK

Symbol

S

R

Q

QCPulse-triggered for

Master-Slave flip-flops

Positive-edge Triggered Flip-Flops (leading edge)

Negative-edge Triggered Flip-Flops (Trailing edge)

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Storage elements

Introduction to Sequential Circuits Flip-Flops

2

Master-Slave SR Flip-Flop

Symbol

S

R

Q

QCCLK

Master gated gated gated gated

gated gated gated gated

hold hold hold hold

hold hold hold hold Slave

SR

Q

MQ slaveSslaveR

Symbol

S

R

Q

QC

S

R

Q

QC

S

R

Q

QC

S

R

CLK

Q

QMaster Slave

MQ

"Positive-edge triggered"

1nQ +S R 1nQ +C0 0 1 1 X

0 1 0 1 X

0 1 1

nQ1 0 1

nQ1 1 1 1 0 nQ nQ

Forbidden

reset state set state

Function Table of SR latch

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Storage elements

Introduction to Sequential Circuits

3

Symbol of MS-SR Flip-flop

S

R

Q

QC

Timing Constrains

R

wt wtht

sut

S and R may not change

SC

C low pulse width C high pulse width

(master enabled)

(slave enabled)

(master hold)

(slave hold)

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Storage elements

Introduction to Sequential Circuits Master-Slave SR Flip-Flop

4

S

R

Q

QC

S

R

Q

QC

S

R

C

Q

QMaster Slave

M Q

"Pulse triggered" SR flip-flop

Symbol

S

R

Q

QC

C

nQ 1nQ +

Slave enabled

Master enabled

Function Table of M-S SR FF

X 0 1 0 1

last Q last Q 0 1 undef.

0 C R Q

X 0 0 1 1

S

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Storage elements

Introduction to Sequential Circuits Master-Slave SR Flip-Flop

"Negative-edge triggered"

5

Master-Slave D Flip-Flop

D Q

QC

D Q

QC

D

C

Q

QMaster Slave

M Q

Symbol

D Q

QC

Positive-edge triggered D flip-flop

C

nQ 1nQ +

Slave enabled

Master enabled

Master hold Slave hold

Function Table of M-S DFF

0 1 X X

0 1 last Q last Q

0 1

C D Q

Symbol

D Q

QC

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Storage elements

Introduction to Sequential Circuits

6

Negative-edge triggered D flip-flop

D Q

QC

D Q

QC

D

C

Q

QMaster Slave

M Q

Symbol

D Q

QC

Symbol

D Q

QC

C

nQ 1nQ +

Slave enabled

Master enabled

Function Table of M-S DFF

0 1 X X

0 1 last Q last Q

0 1

C D Q

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Storage elements

Introduction to Sequential Circuits Master-Slave D Flip-Flop

7

Edge sensitive SR Flip-Flop

2pdt

1pdt

CC

CLK

Q

QR

SC

delay 1pdt

2pdtCLK

setupt holdt

R,S

C

Stable input

Symbol

S

R

Q

QC

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Storage elements

Introduction to Sequential Circuits

8

Positive-edge Triggered D Flip-flop

(SN7474)

With asynchronous CLEAR* and PRESET* inputs

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Storage elements

Introduction to Sequential Circuits

9

Propagation delays

Timing constraints

Timing specifications for SN7474

Source: The TTL Data Book Vol. 2, Texas Instruments Inc. , 1985 [1]

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Storage elements

Introduction to Sequential Circuits Positive-edge Triggered D Flip-flop

10

D Flip-Flop with scan input

Symbol

D Q

QC

Q

CLK

D TE

TI Q

2-to-1 MUX

Symbol

D Q

QC

TE

TI

Function Table of M-S DFF with scan input

0 1 X X X X

0 1 0 1 last Q last Q

0 1

C D Q

X X 0 1 X X

0 0 1 1 X X

TI TE

The extra scan input is used in ASIC to connect flip-flops in an scan chain for testing purposes.

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Storage elements

Introduction to Sequential Circuits

11

D Flip-Flop with Synchronous Clock Enable input

D Q

QC

Q

CLK D

E

Q

2-to-1 MUX

Symbol

D Q

QCE

Used in field programmable gate array chips (FPGA)

Widely used in Synchronous Sequential State Machines.

CE

nQ 1nQ +

D

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Storage elements

Introduction to Sequential Circuits

12

JK Latch

Assumption : KQR =

QJS =

SR latch Exitation function for SR latch

Function table of gated SR latch 1nQ +S RC

0 0 1 1 X

0 1 0 1 X

0 1 1

nQ1 1 1 1 0 nQ

Forbidden

reset state set state

SR latch

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

nQ nKnJ nS nR

0 0 1 1 0 0 0 0

0 0 0 0 0 1 0 1

0 0 1 1 1 0 1 0

1nQ + nQ nKnJ nS nR 1nQ +

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 0 0 0 1 0 1 0

0 0 0 1 0 0 0 1

0 1 0 0 1 1 1 0

nQ

0

1

nQ

Symbol

J

K

Q

QC

Exitation table

Function table of gated JK latch

1nQ +nJ nK0 0 1 1

0 1 0 1

0 1

nQ

nQset reset

Q

QR

S

CCombinational Logic

J

K

S

R

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Storage elements

Introduction to Sequential Circuits

13

Q

QR

S

C

J

K

C

nandpdw t2t −×<

NOTE !

nandpdw t2t −×>Race-around when C=1 if

n1nnn QQ1KJ =⇒== +

Q

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Storage elements

Introduction to Sequential Circuits JK Latch

14

Master-Slave JK Flip-Flop

Symbol

J

K

Q

QC

Function table of gated M-S JK flip-flop

1nQ +nJ nKX 0 0 1 1

X 0 1 0 1

0 1

nQ

nQ

0 nQ

C

set reset

S

R

Q

QC

S

R

Q

QCK

J QQ

MQ

MQMaster Slave

Should be 1

Should be 0

Inputs must be held valid during entire interval that C is 1.

Q

JK

C

MQ

MQQ 0

1

Violation may lead to wrong output

The problem is solved by using inter- nally edge-triggered D flip-flop.

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Storage elements

Introduction to Sequential Circuits

15

Edge-triggered JK Flip-Flop

D Q

QCCKJ Q

Q

Symbol

J

K

Q

QC

Function table of edge-triggered J-K flip-flop

1nQ +K C 1nQ +JX X 0 1 0 1

0 1

0 1

nQ

1 0

nQX X 0 0 1 1

nQ

nQ

nQ

nQ

nQnQ

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Storage elements

Introduction to Sequential Circuits

16

T=1 (toggle) Flip-Flop

T flip-flop changes state on every active clock edge (positive or negative).

TQ

D Q

QC

Q

QT

J

K

Q

QC

Q

QT

1

Symbol

Q

QT

Q

Q

Two different implementations of Toggle flip-flop

J=K=T=1 flip-flop

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Storage elements

Introduction to Sequential Circuits

17

Storage elements

Introduction to Sequential Circuits

n1n QQ =+

n1n QQ =+

0Tn =

1Tn =

J

K

Q

QC

Q

Q

TCLOCK

Clocked T flip-flop

Symbol

Q

Q

T Q

QC

0 0 1 1

0 1 0 1

0 1 1 0

nT nQ 1nQ +

Exitation table of clocked T flip-flop

T

QC

Clocked T Flip-Flop

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T Flip-Flop with Enable Input

Symbol

Q

QT

Q

Q

E

Two different implementations of T flip-flop with Enable control

D Q

QC

Q

QT

E D Q

QC

Q

QTE

1 0

TQ

E

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Storage elements

Introduction to Sequential Circuits

19

Register

The group of edge-triggered D flip-flops

Common clock and clear/preset controls

(4, 8, 16)

[1] SN74175

[1]

SN74273

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Storage elements

Introduction to Sequential Circuits

20

21

The End