Slide 1

Flip-Flops Basic concepts Slide 2 1/50A. Yaicharoen2 Flip-Flops A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) 3 classes of flip-flops latches: outputs respond immediately while enabled (no timing control) pulse-triggered flip-flops: outputs response to the triggering pulse edge-triggered flip-flops: outputs responses to the control input edge Slide 3 1/50A. Yaicharoen3 Conventions The circuit is set means output = 1 The circuit is reset means output = 0 Flip-flops have two output Q and Q or (Q and Q) Due to time related characteristic of the flip- flop, Q and Q (or Q) are usually represented as followed: Q t or Q: present state Q t+1 or Q + : next state Slide 4 1/50A. Yaicharoen4 4 Types of Flip-Flops SR flip-flopJK flip-flop D flip-flopT flip-flop Slide 5 1/50A. Yaicharoen5 SR Latch An SR (or set-reset) latch consists of S (set) input: set the circuit R (reset) input: reset the circuit Q and Q output: output of the SR latch in normal and complement form Application example: a switch debouncer Slide 6 1/50A. Yaicharoen6 SR latch Slide 7 1/50A. Yaicharoen7 An application of the SR latch (a) Effects of contact bounce. (b) A switch debouncer. Slide 8 1/50A. Yaicharoen8 latch Slide 9 1/50A. Yaicharoen9 Gated SR latch (c)(c) Slide 10 1/50A. Yaicharoen10 Gated D latch Slide 11 1/50A. Yaicharoen11 Timing Consideration When using a real flip-flop, the following information is needed to be considered: propagation delay (t pLH, t pHL ) - time needed for an input signal to produce an output signal minimum pulse width (t w(min) ) - minimum amount of time a signal must be applied setup and hold time (t su, t h ) - minimum time the input signal must be held fixed before and after the latching action Slide 12 1/50A. Yaicharoen12 Propagation delays in an SR latch Slide 13 1/50A. Yaicharoen13 Timing diagram for an SR latch Slide 14 1/50A. Yaicharoen14 Minimum pulse width constraint Slide 15 1/50A. Yaicharoen15 Timing diagram for a gated D latch Slide 16 1/50A. Yaicharoen16 Unpredictable response in a gated D latch Slide 17 1/50A. Yaicharoen17 Master-slave SR flip-flop Slide 18 1/50A. Yaicharoen18 Timing diagram for a master-slave SR flip-flop Slide 19 1/50A. Yaicharoen19 Master-slave JK flip-flop Slide 20 1/50A. Yaicharoen20 Timing diagram for master-slave JK flip-flop Slide 21 1/50A. Yaicharoen21 Master-slave D flip-flop Slide 22 1/50A. Yaicharoen22 Master-slave T flip-flop Slide 23 1/50A. Yaicharoen23 Positive-edge-triggered D flip-flop Slide 24 1/50A. Yaicharoen24 Timing diagram for a positive-edge-triggered D flip-flop Slide 25 1/50A. Yaicharoen25 Negative-edge-triggered D flip-flop Slide 26 1/50A. Yaicharoen26 Asynchronous Inputs do not require the presence of a control signal preset (PR) - set the flip-flop clear (CLR) - reset the flip-flop useful to bring a flip-flop to a desired initial state Slide 27 1/50A. Yaicharoen27 Positive-edge-triggered D flip-flop with asynchronous inputs Slide 28 1/50A. Yaicharoen28 Positive-edge-triggered JK flip-flop Slide 29 1/50A. Yaicharoen29 Positive-edge-triggered T flip-flop Slide 30 1/50A. Yaicharoen30 Master-slave JK flip-flop with data lockout Slide 31 1/50A. Yaicharoen31 Characteristic Equations algebraic descriptions of the next-state table of a flip-flop constructing from the Karnaugh map for Q t+1 in terms of the present state and input Slide 32 1/50A. Yaicharoen32 Characteristic equations