February 15, 2002D Flip-Flops Lecture 17 -- Page 1 ECEn 224 Winter 2002 D Flip-Flops Objectives...
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February 15, 2002 D Flip-Flops Lecture 17 -- Page 1 ECEn 224 Winter 200 2 D Flip-Flops Objectives • Explain the operation of D flip- flops • Understand how reset and preset inputs can be added to any flip-flop • Generate the next state equations and state tables for all types of flip-flops
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Transcript of February 15, 2002D Flip-Flops Lecture 17 -- Page 1 ECEn 224 Winter 2002 D Flip-Flops Objectives...
February 15, 2002 D Flip-FlopsLecture 17 -- Page 1
ECEn 224 Winter 2002
D Flip-FlopsObjectives
• Explain the operation of D flip-flops
• Understand how reset and preset
inputs can be added to any flip-flop
• Generate the next state equations
and state tables for all types of flip-
flops
February 15, 2002 D Flip-FlopsLecture 17 -- Page 2
ECEn 224 Winter 2002
D Flip-Flops
Set to the state of the D input on clock transition
FlipFlop
Q’
D Q
CK denotes a clock input
denotes transition onhigh to low
February 15, 2002 D Flip-FlopsLecture 17 -- Page 3
ECEn 224 Winter 2002
D Flip-Flops
Set to the state of the D input on clock transition
FlipFlop
Q’
D Q
CK
Q+ = D
D Q Q+
0 0 00 1 01 0 11 1 1
February 15, 2002 D Flip-FlopsLecture 17 -- Page 4
ECEn 224 Winter 2002
D Flip-Flops
time
Clock
D
Q
FlipFlop
Q’
D Q
CK
February 15, 2002 D Flip-FlopsLecture 17 -- Page 5
ECEn 224 Winter 2002
D Flip-Flops(Typical)
P
P'S
R
R
S
Q
Q'
Clock
D
February 15, 2002 D Flip-FlopsLecture 17 -- Page 6
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
11
0
00
01
1
time
Clock
P
P’
Q
Q’
0
= 0
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 7
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
1
0
0
01
1
time
Clock
P
P’
Q
Q’
0
0
1
01
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 8
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
1
0
0
01
1
time
Clock
P
P’
Q
Q’
0
0110
01
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 9
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
0
0
01
time
Clock
P
P’
Q
Q’
0
10
1
10
10
1
D=0
01
February 15, 2002 D Flip-FlopsLecture 17 -- Page 10
ECEn 224 Winter 2002
D Flip-Flop
0
01
time
Clock
P
P’
Q
Q’
0
1
10
10
10
01
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 11
ECEn 224 Winter 2002
D Flip-Flop
0
01
time
Clock
P
P’
Q
Q’
0
1
10
0
0
01
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 12
ECEn 224 Winter 2002
D Flip-Flop
0
01
time
Clock
P
P’
Q
Q’
0
10
0
0
1
1
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 13
ECEn 224 Winter 2002
D Flip-Flop
0
01
time
Clock
P
P’
Q
Q’
0
10
0
0
1
10
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 14
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
0
01
time
Clock
P
P’
Q
Q’
0
0
0
1
01
10
101
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 15
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
0
1
time
Clock
P
P’
Q
Q’
0
0
0
1
01
0
01
101
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 16
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
0
time
Clock
P
P’
Q
Q’
0
0
0
1
0
01
0
1
10
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 17
ECEn 224 Winter 2002
P
P'S
R
R
S
Q
Q'
Clock
D
D Flip-Flop
time
Clock
P
P’
Q
Q’
0
0
0
1
0
0
1
101
01
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 18
ECEn 224 Winter 2002
D Flip-Flop
time
Clock
P
P’
Q
Q’
0
0
0
1
0
0
1
1
01
0
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 19
ECEn 224 Winter 2002
D Flip-Flop
time
Clock
P
P’
Q
Q’
0
0
0
1
0
0
1
1 0
1
P
P'S
R
R
S
Q
Q'
Clock
D
1
D=0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 20
ECEn 224 Winter 2002
• A reset or clear input is added to many flip-flops for convenience
• This overrides other inputs and forces Q to 0• indicates that the reset is active low (reset
on CLR = 0)
D Flip-Flop with Reset Input
Q’ Q
CK D
CLRClear
February 15, 2002 D Flip-FlopsLecture 17 -- Page 21
ECEn 224 Winter 2002
J-K Flip-Flop with Reset and Preset
• A preset line is added to force a flip-flops to Q = 1
• This overrides other inputs• Clear and preset should not be active
at the same time
Q’ Q
CK J
CLRClear
K
PREThis J-K flip-flop
operates normallyCLR = 1 and PRE = 0
February 15, 2002 D Flip-FlopsLecture 17 -- Page 22
ECEn 224 Winter 2002
Flip-Flop Registers
• Flip-flops are grouped to form data registers• Clear and preset are for designer convenience
in initializing registers
Q’ Q
CK D
CLR
Clear
Q’ Q
CK D
CLR
Q’ Q
CK D
CLR
Q’ Q
CK D
CLR
Clock
Q 1 Q 2 Q 3 Q 4
D 1 D 2 D 3 D 4Data In
Data Out
February 15, 2002 D Flip-FlopsLecture 17 -- Page 23
ECEn 224 Winter 2002
S R Q Q+ T Q Q+ J K Q Q+ D Q Q+
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 1 1 0 0 1 1 0 1 0
0 1 0 0 1 0 1 0 1 0 0 1 0 1
0 1 1 0 1 1 0 0 1 1 0 1 1 1
1 0 0 1 1 0 0 1
1 0 1 1 1 0 1 1
1 1 0 § 1 1 0 1
1 1 1 § 1 1 1 0
Characteristic Equations
Q+ = S + R’Q(SR = 0)
Q+ = T QQ+ = TQ’ + Q’T
Q+ = JQ’ + K’Q
Q+ = D
§ Inputs not allowed
Set-Reset Trigger J-K D
February 15, 2002 D Flip-FlopsLecture 17 -- Page 24
ECEn 224 Winter 2002
Summary
• Explain the operation of D flip-flops
• Understand how reset and preset
inputs can be added to any flip-flop
• Generate the next state equations
and state tables for all types of flip-
flops
