Flip Flops
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Transcript of Flip Flops
![Page 1: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/1.jpg)
Digital ElectronicsDigital Electronics
Flip-Flops
![Page 2: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/2.jpg)
Objectives
• Draw the symbol for the D-Latch and D Flip Flop.
• Given a D flip flop and input waveforms, draw the output waveform for Q.
• Given a J-K flip flop and input waveforms, draw the output waveform for Q.
• Define “Asynchronous” and “Synchronous”.
• Given a J-K flip flop, identify the synchronous and asynchronous inputs.
![Page 3: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/3.jpg)
FLIP-FLOP TYPESRS FLIP FLOP (Reset/Set) a.k.a. Set/Clear
•Most basic flip flop can be made by cross coupling NAND or NOR gates
•Activating Set and Reset is invalid
T Flip Flop (Toggle)
•Output toggles on each clock pulse
•Q output divides clock frequency in half
D Flip Flop (Data or Delay)
•Has only a single data input and clock input
•Input transfers to output on clock pulse
J-K Flip Flop
•Universal, can make all other flip flops
•Has no prohibited states
S
RCLK
Q
Q
CLK
D Q
Q
TQ
Q
J
KCLK
Q
Q
![Page 4: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/4.jpg)
POSITIVE LEVEL TRIGGEREDD FLIP-FLOP
EN
D Q
Q
Q
Q NOT
D
CLK
D
CLK
Symbol:
Truth Table:DEN Q*
No change0 X1 01 1 1
0
*Q follows D inputwhile EN is HIGH
![Page 5: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/5.jpg)
POSITIVE LEVEL TRIGGEREDD FLIP-FLOP
TIMING DIAGRAMS
EN
D Q
Q
DEN Q*No change0 X
1 01 1 1
0
*Q follows D inputwhile EN is HIGH
C
D
Q
C
D
Q
C
D
Q
![Page 6: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/6.jpg)
POSITIVE EDGE TRIGGEREDD FLIP-FLOP
TIMING DIAGRAMS
CLK
D Q
Q
DCLK Q*No changeX
01 1
0
*Q follows D inputwhen CLK is HIGH
C
D
Q
C
D
Q
C
D
Q
![Page 7: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/7.jpg)
NEGATIVE EDGE TRIGGEREDT FLIP-FLOP Symbol:
Truth Table:
TQ
Q•Output toggles on each clock pulse
•Q output divides clock frequency in half
•Usually made with JK Flip Flop
CLK Q
Q O
MEANS THAT THE NEW VALUE OF Q WILL BE THEINVERSE OF THE VALUE IT HAD PRIOR TO THE NGT
Q OQ=
CLK
D Q
Q
![Page 8: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/8.jpg)
NEGATIVE EDGE TRIGGEREDT FLIP-FLOP
Timing Diagrams
TQ
Q
CLK Q
Q O
MEANS THAT THE NEW VALUE OF Q WILL BE THEINVERSE OF THE VALUE IT HAD PRIOR TO THE NGT
Q OQ=
T
Q
T
Q
![Page 9: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/9.jpg)
J-K FLIP-FLOP
J
KCLK
Q
Q
•UNIVERSAL Flip Flop can make all others from JK (T, D and RS)
•The “J” input acts like SET, K acts like RESET
•No illegal state, activating both inputs causes Q to TOGGLE
![Page 10: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/10.jpg)
J-K FLIP-FLOPSymbol:
Truth Table:
J
KCLK
Q
Q
Q
QNOT
J
K
CLOCK
CLK J K0
QX X
1NO CHG
X X
0
X
0
NO CHGX NO CHG
0 NO CHG1
1 01 1
SETRESET
TOGGLE
MODEHOLDHOLDHOLD
HOLD01Q O
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NEGATIVE EDGE TRIGGEREDJ-K FLIP-FLOP
Timing DiagramsJ
KCLK
Q
Q
CLK J K Q00
0 NO CHG1
1 01 1
01Q O
C
J
K
Q
C
J
K
Q
![Page 12: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/12.jpg)
POSITIVE EDGE TRIGGEREDJ-K FLIP-FLOP
Timing DiagramsJ
KCLK
Q
Q
CLK J K Q00
0 NO CHG1
1 01 1
01Q O
C
J
K
Q
C
J
K
Q
C
J
K
Q
![Page 13: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/13.jpg)
ASYNCHRONOUS OVERRIDES
J
KCLK
Q
Q
CLR
PREAsynchronous Inputs a.k.a. Overide Inputs operate independent of the control and clock inputs
PRESET
Active-low override Q=1
overrides all other inputs
PRE
CLR CLEAR
Active-low override Q=0
overrides all other inputs
![Page 14: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/14.jpg)
J-K FLIP-FLOPASYNCHRONOUS OVERRIDES
J
KCLK
Q
Q
CLR
PRE
0
1 0
PRE1
0 Ambiguous (not used)
Q=0 independent of synchronous inputs
Q*No effect; FF can respond to J, K, and CLK
Q=1 independent of synchronous inputs
*CLK can be in any state
CLR1
0 1
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J-K FLIP-FLOP
Symbol:
Mode of Operation Inputs Outputs PS Clr Clk J K Q Q’
Asynchronous set 0 1 x x x 1 0
Asynchronous reset 1 0 x x x 0 1Prohibited 0 0 x x x 1 1-------------------------------------------------------------------------Hold 1 1 0 0 no changeReset 1 1 0 1 0 1Set 1 1 1 0 1 0Toggle 1 1 1 1 opposite
x = Irrelevant = H-to-L transition of clock pulse
Truth Table:
J Q
K QClk __
![Page 16: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/16.jpg)
J-K FLIP-FLOPASYNCHRONOUS OVERRIDES
Timing Diagrams
J
KCLK
Q
Q
CLR
PRE
0
1 0
PRE1
0 IllegalQ=1
QNo effectQ=0
CLR1
0 1 J
K
Q
CLOCK
PRESET
CLEAR
![Page 17: Flip Flops](https://reader035.fdocuments.us/reader035/viewer/2022081816/544df33ab1af9fbb1e8b46df/html5/thumbnails/17.jpg)
1. The “D” in “D flip flop” stands for _________ or _________ .
2. With a D flip flop, Q follows _____ when triggered by the clock.
3. The “J” input on a J-K flip flop acts like what input on an RS Latch?
4. The “K” input on a J-K flip flop acts like what input on an RS Latch?
5. What inputs on a J-K flip flop are the Asynchronous inputs?
6. What inputs on a J-K flip flop are the Synchronous inputs?
TEST
Data Delay
D
Set
Reset
Preset/Set Clear/Reset
J & K