Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal...

Chapter 10Chapter 10

Flip-Flops and RegistersFlip-Flops and Registers

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ObjectivesObjectives

You should be able to:You should be able to: Explain the internal circuit operation of Explain the internal circuit operation of

S-R and gated S-R flip-flops.S-R and gated S-R flip-flops. Compare the operation of D latches and Compare the operation of D latches and

D flip-flops by using timing diagrams.D flip-flops by using timing diagrams. Describe the difference between pulse-Describe the difference between pulse-

triggered and edge-triggered flip-flops.triggered and edge-triggered flip-flops.

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ObjectivesObjectives

(Continued)(Continued) Explain the theory of operation of Explain the theory of operation of

master-slave devices.master-slave devices. Connect IC J-K flip-flops as toggle and D Connect IC J-K flip-flops as toggle and D

flip-flops.flip-flops. Use timing diagrams to illustrate the Use timing diagrams to illustrate the

synchronous and asynchronous operation synchronous and asynchronous operation of J-K flip-flops.of J-K flip-flops.

Use VHDL to design flip-flops for CPLD Use VHDL to design flip-flops for CPLD implementation. implementation.

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S-R Flip-FlopS-R Flip-Flop Data storage circuitData storage circuit Cross-coupled NOR schemeCross-coupled NOR scheme Asynchronous set and resetAsynchronous set and reset

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S-R Flip-FlopS-R Flip-Flop

Function tableFunction table

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S-R Flip-FlopS-R Flip-Flop Cross-coupled NAND schemeCross-coupled NAND scheme

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Function tableFunction table

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Both true and complemented Q Both true and complemented Q outputsoutputs

Symbols for a Symbols for a S-RS-R FF FF

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S-R Flip-Flop Timing S-R Flip-Flop Timing AnalysisAnalysis

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S-R Flip-Flop ApplicationS-R Flip-Flop Application Storage register to Storage register to rememberremember time of time of

day when a temperature limit switch day when a temperature limit switch goes high.goes high.

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Gated S-R Flip-FlopGated S-R Flip-Flop Asynchronous – output responds Asynchronous – output responds

immediately to inputimmediately to input Synchronous – output responds in step Synchronous – output responds in step

with a control inputwith a control input

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Gated S-R Flip-FlopGated S-R Flip-Flop

Function table and symbolFunction table and symbol

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Gated D Flip-FlopGated D Flip-Flop DataData flip-flop with example inputs flip-flop with example inputs

and outputsand outputs

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Discussion PointDiscussion Point

How will the complement of an How will the complement of an output differ from the output?output differ from the output?

Explain the difference between Explain the difference between synchronous and asynchronous synchronous and asynchronous inputs.inputs.

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D Latch: 7475 IC;D Latch: 7475 IC;VHDL DescriptionVHDL Description

Four Four transparent D transparent D latcheslatches

Logic symbol Logic symbol and pin and pin configurationconfiguration

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D Latch: 7475 IC;D Latch: 7475 IC;

Function table shows that Q output Function table shows that Q output follows D (transparent) if enable line follows D (transparent) if enable line is HIGH.is HIGH.

When E is low, Q is latched to prior When E is low, Q is latched to prior value of D.value of D.

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VHDL Description of a D VHDL Description of a D LatchLatch

Block design fileBlock design file


VHDL design fileVHDL design file


Simulation fileSimulation file

D Flip-Flop: 7474 ICD Flip-Flop: 7474 ICVHDL DescriptionVHDL Description

Positive edge-triggered devicePositive edge-triggered device Transitions of output occur at the rising Transitions of output occur at the rising

edge of input trigger pulseedge of input trigger pulse Clock signal usually used as trigger Clock signal usually used as trigger

pulse instead of an enable linepulse instead of an enable line

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7474 Integrated Circuit D 7474 Integrated Circuit D Flip-FlopFlip-Flop

Logic symbol and pin configurationLogic symbol and pin configuration

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Integrated Circuit D Integrated Circuit D Flip-FlopFlip-Flop

Positive edge-detection circuitPositive edge-detection circuit

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Integrated Circuit D Flip-Integrated Circuit D Flip-FlopFlop

Synchronous inputsSynchronous inputs D (Data)D (Data) CCpp (Clock) (Clock)

Asynchronous inputsAsynchronous inputs SSDD (Set) (Set)

RRDD (Reset) (Reset)

Setup TimeSetup Time D must be stable before transition of CD must be stable before transition of Cpp

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Integrated Circuit D Flip-Integrated Circuit D Flip-FlopFlop

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VHDL Description of a VHDL Description of a D Flip-FlopD Flip-Flop

Block design fileBlock design file

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Listing fileListing file

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Flow chartFlow chart

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Simulation fileSimulation file

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Master-Slave J-K Flip-Master-Slave J-K Flip-FlopFlop

Toggle modeToggle mode Switches to opposite state at active Switches to opposite state at active

clock edgeclock edge Master-slaveMaster-slave

Master receives data while input Master receives data while input trigger is HIGHtrigger is HIGH

Slave receives data from master and Slave receives data from master and outputs it when clock goes LOWoutputs it when clock goes LOW

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Function TableFunction Table

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Equivalent circuit and logic symbolEquivalent circuit and logic symbol

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Enable/disable operation of the CEnable/disable operation of the CPP line line

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Pulse-triggered (level-triggered)Pulse-triggered (level-triggered) Input data are read during entire time Input data are read during entire time

clock pulse is at a HIGH levelclock pulse is at a HIGH level Noise can appear on J and K while CP is Noise can appear on J and K while CP is

high high Called “Ones catching”Called “Ones catching”

Eliminated by newer designs using edge Eliminated by newer designs using edge triggeringtriggering

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Edge-Triggered J-K Flip-Edge-Triggered J-K Flip-FlopFlop

Accepts data on the J and K inputs Accepts data on the J and K inputs only only at the active clock edgeat the active clock edge

Symbols for positive and negative Symbols for positive and negative edge triggered J-K FFsedge triggered J-K FFs

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Edge-Triggered J-K Flip-Edge-Triggered J-K Flip-FlopFlop

Function TableFunction Table

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VHDL Description of an VHDL Description of an Edge-Triggered J-K Flip-Edge-Triggered J-K Flip-

FlopFlop Block design fileBlock design file

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FlopFlop VHDL VHDL

design filedesign file

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FlopFlop FlowchartFlowchart

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FlopFlop Simulation fileSimulation file

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Discussion PointDiscussion Point

How are pulse triggered (level How are pulse triggered (level triggered) devices different from triggered) devices different from edge triggered devices?edge triggered devices?

What is ones catching?What is ones catching? Identify the synchronous and Identify the synchronous and

asynchronous inputs on a JK flip-flop asynchronous inputs on a JK flip-flop logic symbollogic symbol

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Integrated Circuit J-K Integrated Circuit J-K Flip-FlopFlip-Flop

7476 – positive pulse-triggered7476 – positive pulse-triggered 74LS76 - negative edge-triggered74LS76 - negative edge-triggered

Logic symbol and pin configurationLogic symbol and pin configuration

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Integrated Circuit J-K Integrated Circuit J-K Flip-FlopFlip-Flop To form a D flip-flop add an To form a D flip-flop add an

inverterinverter

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To form a toggle flip-flop tie inputs To form a toggle flip-flop tie inputs HIGHHIGH

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Using an Octal D Flip-Using an Octal D Flip-Flop in a Flop in a

Microcontroller Microcontroller ApplicationApplication Octal ICs - eight on a chipOctal ICs - eight on a chip

8-bit register8-bit register 74HCT273 logic diagram74HCT273 logic diagram

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Using an Octal D Flip-Using an Octal D Flip-Flop in a Flop in a

Microcontroller Microcontroller ApplicationApplication The 74HCT273 as an update and hold The 74HCT273 as an update and hold

registerregister

Figure 10-45

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Altera’s LPM Flip-FlopAltera’s LPM Flip-Flop

Quartus II provides a general-Quartus II provides a general-purpose flip-flop called purpose flip-flop called LPM_FLPM_F

Found in Library of Parameterized Found in Library of Parameterized Modules subdirectory Modules subdirectory /megafunctions/storage/megafunctions/storage

Can be used to implement several Can be used to implement several types of flip-flopstypes of flip-flops

Altera’s LPM Flip-FlopAltera’s LPM Flip-Flop LPM D flip-flop block design fileLPM D flip-flop block design file

Altera’s LPM Flip-FlopAltera’s LPM Flip-Flop LPM D flip-flop simulation fileLPM D flip-flop simulation file

Altera’s LPM Flip-FlopAltera’s LPM Flip-Flop LPM octal D flip-flop block design LPM octal D flip-flop block design

filefile

Altera’s LPM Flip-FlopAltera’s LPM Flip-Flop LPM octal D flip-flop simulation fileLPM octal D flip-flop simulation file

SummarySummary

The S-R flip-flop is a single-bit data The S-R flip-flop is a single-bit data storage circuit that can be storage circuit that can be constructed using basic gates.constructed using basic gates.

Adding gate enable circuitry to the Adding gate enable circuitry to the S-R flip-flop makes it S-R flip-flop makes it synchronoussynchronous. . This means that it will operate only This means that it will operate only under the control of a clock or under the control of a clock or enable signal.enable signal.

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SummarySummary

The D flip-flop operates similar to The D flip-flop operates similar to the S-R, except it has only a single the S-R, except it has only a single data input, D.data input, D.

The 7475 is an integrated-circuit D The 7475 is an integrated-circuit D latch. The output (Q) follows D latch. The output (Q) follows D while the enable (E) is HIGH. When while the enable (E) is HIGH. When E goes LOW, Q remains latched.E goes LOW, Q remains latched.

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SummarySummary

The 7474 is an integrated-circuit D The 7474 is an integrated-circuit D flip-flop. It has two synchronous flip-flop. It has two synchronous inputs, D and Cinputs, D and Cpp, and two , and two asynchronous inputs, Sasynchronous inputs, SDD and R and RDD. Q . Q changes to the level of D at the changes to the level of D at the positive edge of Cpositive edge of Cpp. Q responds . Q responds immediately to the asynchronous immediately to the asynchronous inputs regardless of the synchronous inputs regardless of the synchronous operations.operations.

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SummarySummary

The J-K flip-flop differs from the S-R The J-K flip-flop differs from the S-R flip-flop because it can also perform a flip-flop because it can also perform a toggle operation. Toggling means toggle operation. Toggling means that Q flips to its opposite state.that Q flips to its opposite state.

The master-slave J-K slip-flop consists The master-slave J-K slip-flop consists of two latches: a master that of two latches: a master that receives data while the clock trigger receives data while the clock trigger is HIGH, and a slave that receives is HIGH, and a slave that receives data from the master and outputs it data from the master and outputs it to Q when the clock goes LOW.to Q when the clock goes LOW.

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SummarySummary

The 74LS76 is an edge-triggered J-K The 74LS76 is an edge-triggered J-K flip-flop IC. It has synchronous and flip-flop IC. It has synchronous and asynchronous inputs. The 7476 is asynchronous inputs. The 7476 is similar, except it is a pulse-triggered similar, except it is a pulse-triggered master-slave type.master-slave type.

The 74HCT273 is an example of an The 74HCT273 is an example of an octal D flip-flop. It has eight D flip-octal D flip-flop. It has eight D flip-flops in a single IC package, making flops in a single IC package, making it ideal for microprocessor it ideal for microprocessor applications.applications.

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SummarySummary

The Quartus II software provides a The Quartus II software provides a general-purpose flip-flop in the general-purpose flip-flop in the LPM subdirectory that can be LPM subdirectory that can be used to implement multi-bit D and used to implement multi-bit D and toggle flip-flops.toggle flip-flops.

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Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal...

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