Post on 13-Jan-2016
SEQUENTIAL CIRCUITSComponent Design and Use
Register with Parallel Load
Register: Group of Flip-Flops Ex: D Flip-Flops Holds a Word of Data Loads in Parallel on Clock
Transition Asynchronous Clear (Reset)
Register with Load Control
Load Control = 1 New data loaded
on next positiveclock edge
Load Control = 0 Old data reloaded
on next positiveclock edge
Shift Registers Cascade chain of Flip-Flops Bits travel on Clock edges Serial in – Serial out, can also have parallel load /
read
Parallel Data Transfer°All data transfers on rising clock edge
°Data clocked into register Y
Parallel versus Serial
Serial communications is defined as Provides a binary number as a sequence of binary digits,
one after another, through one data line.
Parallel communications Provides a binary number through multiple data lines at
the same time.
parallel inputs
parallel outputs
serial transmission
Shift register application
Parallel-to-serial conversion for serial transmission
Serial Transfer Data transfer one bit at a time Data loopback for register A
Time
T0
T1
T2
T3
T4
Reg A
1011
1101
1110
0111
1011
Reg B
0011
1001
1100
0110
1011
Serial Transfer of Data Transfer from register X to register Y
(negative clock edges for this example)
D Q D Q D Q D QIN
OUT1 OUT2 OUT3 OUT4
CLK
OUT
Pattern recognizer Combinational function of input samples
in this case, recognizing the pattern 1001 on the single input signal
IN OUT1 OUT2 OUT3 OUT4 OUT
1 1 0 0 0 0 0 2 0 1 0 0 0 0 3 0 0 1 0 0 0 4 1 0 0 1 0 0 5 0 1 0 0 1 1
Serial Addition (D Flip-Flop) Slower than
parallel Low cost Share fast
hardware onslow data
Serial Addition (D Flip-Flop) Only one full adder Reused for each
bit Start with low-
order bit addition Note that carry (Q)
is saved Add multiple
values. New values
placed in shift register B
Serial Addition (D Flip-Flop)
Shift control used to stop addition
Generally not a good idea to gate the clock
Shift register can be of arbitrary length
FA is built from combin. logic
Universal Shift Register
Clear Clock Shift
Right Left
Load Read Control
Counters
Counter: A register that goes through a prescribed series of states
Binary counter Counter that follows a binary sequence N bit binary counter counts in binary from n to 2n-1
Ripple counters triggered by initial Count signal Applications:
Watches Clocks Alarms Web browser refresh
Binary Ripple Counter
Reset signal sets all outputs to 0
Count signal toggles output of low-order flip flop
Low-order flip flop provides trigger for adjacent flip flop
Not all flops change value simultaneously Lower-order flops change first
Focus on D flip flop implementation
Another Asynchronous Ripple Counter
° Similar to T flop example on previous slide
Asynchronous Counters
Each FF output drives the CLK input of the next FF.
FFs do not change states in exact synchronism with the applied clock pulses.
There is delay between the responses of successive FFs.
Ripple counter due to the way the FFs respond one after another in a kind of rippling effect.
A3 A2
0 00 00 00 00 10 11 01 0
A1
00110000
A0
01010101
Synchronous counters
Synchronous(parallel) counters All of the FFs are triggered
simultaneously by the clock input pulses.
All FFs change at same time
Remember If J=K=0, flop maintains value If J=K=1, flop toggles
Most counters are synchronous in computer systems.
Can also be made from D flops Value increments on positive
edge Note that low-order bit (A0)
toggles on each clock cycle
Synchronous UP/Down counters
Up/Down Counter can either count up or down on each clock cycle
Up counter counts from 0000 to 1111 and then changes back to 0000
Down counter counts from 1111 to 0000 and then back to 1111
Counter counts up or down each clock cycle
Output changes occur on clock rising edge
Counters with Parallel Load
Counters with parallel load can have a preset value
Load signal indicates that data (I3…I0) should be loaded into the counter
Clear resets counter to all zeros
Carry output could be used for higher-order bits
Counters with Parallel Load
Clear Clk Load Count Function 0 X X X Clear to 0 1 ↑ 1 X Load inputs 1 ↑ 0 1 Count 1 ↑ 0 0 No Change
Function Table
If Clear is asserted (0), the counter is cleared
If Load is asserted data inputs are loaded
If Count asserted counter value is incremented
Binary Counter with Parallel Load and Preset
• Presettable parallel counter with asynchronous preset.
If PL’ = 0, load P into flops
Binary Counter with Parallel Load and Preset
• Commercial version of binary counter
MEMORY
Memory is a collection of storage cells with associated input and output circuitry Possible to read and write cells
Random access memory (RAM) contains words of information
Data accessed using a sequence of signals Leads to timing waveforms
Decoders are an important part of memories Selects specific data in the RAM
Static RAM loses values when circuit power is removed.
Preliminaries
RAMs contain a collection of data bytes A collection of bytes is called a word A sixteen bit word contains two bytes Capacity of RAM device is usually described in bytes
(e.g. 16 MB) Write operations write data to specific words Read operations read data from specific words Note: new notation for OR gate
RAM Interface Signals Data input and output
lines carry data Memory contains 2k
words k address lines select
one word out of 2k
Read asserted when data to be transferred to output
Write asserted when data input to be stored
Preliminaries Address Data
00000000
00000001
00000002
.
.
.
.
.
.
.
.
.
.
FFFFFFFD
FFFFFFFE
FFFFFFFF
Memory – big array of data
Each address refers to one word/byte of data
You can read or write the data
Random Access Memory Fundamentals
Lets consider a simple RAM chip 8 words of 2 bytes each (each word is 16 bits) How many address bits do we need?
01010000 1110011011001100 1111111100000000 1010101001010110 0011111111111111 0000000000000001 1000000001010101 1100110000000000 11111111
word
Pick one of 8 locationsDec Binary0 000 1 0012 0103 0114 1005 1016 1107 111
16 Data and Input signals
____ address signals
Each bit stored in a binary cell
RAM Size
° If memory has 2k words, k address bits are needed
°23 words, 3 address bits
°Address locations are labelled 0 to 2k-1
°Common subscripts:
°Kilo – 210
°Mega – 220
°Giga - 230
Write Operation
1. Apply binary address of word to address lines
2. Apply data bits to data input lines
3. Activate write input
Data output lines unused
Read input signal should be inactive
Delay associated with write
Read Operation
1. Apply binary address of word to address lines
2. Activate read input
Data input lines unusedWrite input signal should be inactive
Delay associated with read
Memory enable used to allow read andwrites
Memory Timing – write operation Memory does not use a clock
Control signals may be generated on clock edges Cycle time – time needed to write to memory If cycle time is 50 ns, 3 clock edges required (T1, T2, T3)
Access time indicates time to read
Address indicates location
Data valid on Data Output following access time
Timing Waveforms – read operation
Multiple clock signals needed for data read in this example* Note ordering of signals (address, mem enable)
Comments about Memory Access and Timing
Most computers have a central processing unit (CPU) Processor generates control signals, address, and data Values stored and then read from RAM
° The timing of the system is very important. • Processor provides data for the cycle time on
writes
• Processor waits for the access time for reads
Types of Random Access Memories
Static random access memory (SRAM) Operates like a collection of latches Once value is written, it is guaranteed to remain in the memory
as long as power is applied Generally expensive Used inside processors (like the Pentium)
Dynamic random access memory (DRAM) Generally, simpler internal design than SRAM Requires data to be rewritten (refreshed), otherwise data is lost Often hold larger amount of data than SRAM Longer access times than SRAM Used as main memory in computer systems
Inside the RAM Device
Address inputs go into decoder Only one output active
Word line selects a row of bits (word)
Data passes through OR gate
Each binary cell (BC) stores one bit
Input data stored if Read/Write is 0
Output data driven if Read/Write is 1
38
Connecting three-state buffers together
You can connect several three-state buffer outputs together if you can guarantee that only one of them is enabled at any time.
Allows us to save some wire and gate costs.
Inside the SRAM Device Basis of each SRAM cell is an S-R latch Note that data goes to both S and R Select enables operation Read/write enables read or write, but not both
Inside the SRAM Device
Note: delay primarily depends on the number of words
Delay not effected by size of words
° How many address bits would I need for 16 words?
Word
Inside the SRAM Device
(a) Logic diagram
Select
S
R
Q
Q
B
RA M cell
C
CB
SelectWordselect2n 2 1
Wordselect2n 2 1
Wordselect0
Wordselect1
S
R
Q
QRA M cell
X
Wordselect0
Data in
Write logic
Read/Write
Bitselect
S
R
Q
Q
X
X
X
Read/Writelogic
Data inData out
Read/Write
Bitselect
(b) Symbol
RA M cell
RA M cell
RA M cell
Data outRead logic
Inside the SRAM Device
Read/
Word select
Read/Writelogic
Data inData out
WriteBitselect
(b) Block diagram
RAM cell
RAM cell
RAM cell
Data input
Chip select
Read/Write
Dataoutput
A3
A2
A1
A0
23
22
21
20
4-to-16Decoder0
123456789
101112131415
A3
A2
A1
A0
Datainput
Dataoutput
(a) Symbol
Read/Write
Memoryenable
16 x 1RAM
43 8
8
16
Making a larger memory We can put
four 64K x 8 chips together to make a 256K x 8 memory.
Two-dimensional decoding
Two-dimensional decoding
Data inputRead/Write
X XX
A1 A0
RAM cell0
RAM cell4
RAM cell8
RAM cell12
Read/Writelogic
Data inData out
Read/Write
Bitselect
RAM cell1
RAM cell5
RAM cell9
RAM cell13
Read/Writelogic
Data inData out
Read/Write
Bitselect
RAM cell2
RAM cell6
RAM cell10
RAM cell14
Read/Writelogic
Data inData out
Read/Write
Bitselect
RAM cell3
RAM cell7
RAM cell11
RAM cell15
Read/Writelogic
Data inData out
Read/Write
Bitselect
Columndecoder
2-to-4 Decoderwith enable
21 20
0 1
Column select
2
Enable
3
Chip select
Dataoutput
Rowselect
Row decoder
A2
A3
X
2-to-4Decoder
20
21
1
2
3
0
Address Multiplexing