Post on 08-Jan-2016
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Flip Flops, RegistersFlip Flops, RegistersNotes:
• No Studios This week
• About lab proto-boards and modules– Must stay in the lab
– You are responsible for your assigned equipment for the entire semester.
Today:
• First Hour: Types of Latches, Flip FlipsLatches, Flip Flips– Section 6.1.4-6.1.6 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Storage and Shift Registers• Section 7.1 of Katz’s Textbook
– In-class Activity #2
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State Diagrams for LatchesState Diagrams for Latches
State Behavior of R-S Latch
Truth Table Summary of R-S Latch Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
Q Q1 1
Q
hold 0 1
unstable
S
0 0 1 1
R
0 1 0 1
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State Diagram: R-S LatchState Diagram: R-S Latch
Theoretical R-S Latch State Diagram
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
Q Q1 1
SR = 0 0
SR = 0 0, 11
SR = 11
SR = 1 0SR = 0 1
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Observed R-S BehaviorObserved R-S Behavior
Q Q Q Q
Q Q
0 1 1 0
0 0
SR = 1 0
SR = 0 1
SR = 0 1
SR = 1 1
SR = 1 0
SR = 1 1
SR = 00, 01 SR = 00, 10
SR = 0 0
SR = 11
SR = 0 0
Very difficult to observe R-S Latch in the 1-1 state
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition"
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Making Other LatchesMaking Other Latches
J K Q Q+
0 0 0 0 HOLDHOLD0 0 1 10 1 0 0 RESETRESET0 1 1 01 0 0 1 SETSET1 0 1 11 1 0 1 TOGGLETOGGLE1 1 1 0
NEXT STATE TABLENEXT STATE TABLE
Simplify by coupling inputs
i.e., one input i.e., one input determinesdetermines the other the other
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D LatchD Latch
J K Q Q+
0 0 0 0 HOLDHOLD0 0 1 10 1 0 0 RESETRESET0 1 1 01 0 0 1 SETSET1 0 1 11 1 0 1 TOGGLETOGGLE1 1 1 0
NEXT STATE TABLE
NEXT STATE TABLENEXT STATE TABLE
D Q Q+
0 0 0 RESETRESET0 1 01 0 1 SETSET1 1 1
Let Let J = D, K = DJ = D, K = D
D
Also called D flip-flop if edge-triggered
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T LatchT Latch
J K Q Q+
0 0 0 0 HOLDHOLD0 0 1 10 1 0 0 RESETRESET0 1 1 01 0 0 1 SETSET1 0 1 11 1 0 1 TOGGLETOGGLE1 1 1 0
NEXT STATE TABLE Let J = T, K = TLet J = T, K = T
T Q Q+
0 0 0 HOLDHOLD0 1 11 0 1 TOGGLETOGGLE1 1 0
NEXT STATE TABLENEXT STATE TABLE
T
Also called T flip-flop if edge-triggered
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Timing issues revisitedTiming issues revisited
J
K
Q
\ Q
100 Set Reset Toggle
Problem: Keeps on toggling!
R
S Q
Q
LatchQ
QJ
K
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Master section - clock high
J-K inputs generate P outputs
Master section - clock high
J-K inputs generate P outputs
Slave section - clock low
Ps are unchanging and generate Qs
Slave section - clock low
Ps are unchanging and generate Qs
J-K Master/Slave F-FJ-K Master/Slave F-F
R
S
Q
Q
Latch
R
S
Q
Q
Latch
Clock
J
K
Q
Q
P
P
Clock
Two-stage memory element Two-stage memory element Two-stage memory element Two-stage memory element
Two-phase clock operation - Feedback has no effect until next time clock is highTwo-phase clock operation - Feedback has no effect until next time clock is high
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Timing: master-slaveTiming: master-slaveMaster Stage Slave Stage
Sample inputs while clock high Sample inputs while clock low
Uses time to break feedback path from outputs to inputs!Uses time to break feedback path from outputs to inputs!
Correct ToggleOperation
J
R-S Latch
R-S Latch
K R
S
Clk
\Q
Q
\P
P
R
S
\Q
Q
\Q
Q
Master outputs
Slave outputs
Set Reset T oggle 1's
Catch 100
J
K
Clk
P
\ P
Q
\ Q
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Effect of GlitchesEffect of Glitches1's Catching problem: If input = 1 any time during the clock period (even a 0-1-0 glitch), it will be
interpreted as a 1 for computing output designer must use hazard-free logic
Solution: edge-triggered logic called “Flip-flops”
Built from 3 latches
Negative Edge-TriggeredD flipflop
When clock is high: R=S=0 is the Hold state
Q
Q
D
Clk=1
R
S
0
0
D
DD
Holds D when clock goes low
Holds D when clock goes low
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Step-by-Step AnalysisStep-by-Step AnalysisNegative Edge-triggered D Flipflops
Q
Q
D
Clk=0
R
S
D
DD
D
D
D
When clock goes high-to-lowR = D’, S = D
(new data D is latched)
Q
Q
D
Clk=1
R
S
0
0
D
DD
Holds D when clock goes low
Holds D when clock goes low
Initially Clk = 1R = S = 0
(Hold)
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Step-by-Step AnalysisStep-by-Step AnalysisNegative Edge-triggered D Flipflops
Q
Q
D
Clk=0
R
S
D
DD
D
D
D
Q
Q
D'
Clk=0
R
S
D
D
D
D
D' ° D
0
0
1
2
3
4
5
6
If clock remains low, andD changes,
(Previous value of D is held)
When clock goes high-to-lowR = D’, S = D
(new data D is latched)
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Latches vs Flip-FlopsLatches vs Flip-Flops Input/Output Behavior of Latches and Flipflops
Type When Inputs are Sampled When Outputs are ValidUn-clocked always propagation delay from latch input change
level clock high propagation delay from-sensitive (Tsu, Th around input changelatch falling clock edge)
positive edge clock lo-to-hi transition propagation delay fromflipflop (Tsu, Th around rising edge of clock rising clock edge)
negative edge clock hi-to-lo transition propagation delay fromflipflop (Tsu, Th around falling edge of clock falling clock edge)
master/slave clock hi-to-lo transition propagation delay fromflipflop (Tsu, Th around falling edge of clock falling clock edge)
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R-S Clocked Latch: used as storage element in narrow width clocked systems its use is not recommended! however, fundamental building block for other flipflop types
J-K Flipflop: versatile building block can be used to implement D and T FFs usually requires least amount of logic to implement ƒ(in,Q,Q+) but has two inputs with increased wiring complexity
because of 1's catching, never use master/slave J-K FFs edge-triggered varieties exist
D Flipflop: minimizes wires, much preferred in VLSI technologies simplest design technique best choice for storage registers
T Flipflops: don't really exist, constructed from J-K FFs usually best choice for implementing counters
Preset and Clear inputs highly desirable!!
Comparison of FFsComparison of FFs
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TTL schematicsTTL schematics7474
7476
Bubble herefor negative
edge triggereddevice
Timing Diagram:
Behavior the same unless input changes while the clock is high
Edge triggered device sample inputs on the event edge
Transparent latches sample inputs as long as the clock is assertedPositive edge-triggered
flip-flop
Level-sensitive latch
D Q
D Q
C
Clk
Clk
D
Clk
Q
Q
7474
7476
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Do Activity #1 NowDo Activity #1 Now
Q
Q
D
Clk
R
S
D’
D
D
DD
Holds D when clock goes low
Holds D when clock goes low
TYPO!!: For Part (a) start with circle (0, 1)
J K Q Q+
0 0 0 0 HOLDHOLD0 0 1 10 1 0 0 RESETRESET0 1 1 01 0 0 1 SETSET1 0 1 11 1 0 1 TOGGLETOGGLE1 1 1 0
J-K NEXT STATE TABLEJ-K NEXT STATE TABLE
Pages 296-298 of Katz
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Sequential Logic ComponentsSequential Logic Components• Flipflops:Flipflops: most primitive "packaged" sequential circuits• More complex sequential building blocks:
– Storage registers, Shift registers, Counters– Available as components in the TTL Catalog
– RegistersRegisters
» Store a word (4 to 64 bits)
» E.g.: Pentium has several registers
– CountersCounters
» Count thru a sequence of states
» E.g., the seconds display on a clock.
– Both of these have many variations.
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Storage RegistersStorage Registers
• Storage registersStorage registers store data, without changing it.
– A D F/F is a 1-bit storage register.
• A Register FileA Register File stores a group of words of data.
– You specify which word to read or write.
• A Random-Access MemoryRandom-Access Memory is like a large register file. It may store 32MB of data or more.
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Multi-bit Storage RegistersMulti-bit Storage Registers
Clocks in 4 bits in parallel, or resets to 0.Clocks in 4 bits in parallel, or resets to 0.
use D F/Fs in groups to make a multibit registeruse D F/Fs in groups to make a multibit register
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Q1
CLR
D3D2D1D0
171
Q1Q0
Q0
CLK
Q3
Q3
Q2
Q2
1445
12
11
131
15
2
3
7
6
9
10
74171 Quadruple D F/F with Clear74171 Quadruple D F/F with Clear
This stores 4 bits in parallelThis stores 4
bits in parallel
No bubble indicates positive edge
triggered
No bubble indicates positive edge
triggered
The /CLR clears all 4 bits
The /CLR clears all 4 bits
Triangle indicates clock inputTriangle indicates clock input
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Register VariantsRegister Variants
• Sometimes there’s also a LOAD input.
– When LOAD is false, the F/F doesn’t change.
– When LOAD is true during the clock edge, the F/F updates itself.
• Sometimes the outputs are 3-state or open collector.
– This allows several registers to be connected to the same output wire
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D3
D6Q5
Q2
377
Q1Q0
Q3
ENCLK
Q6
Q4
Q7
D5
D2D1D0
D4
D7
1
3478
13141718
11
256912151619
74377 Octal D F/Fs with Enable74377 Octal D F/Fs with Enable
Stores an 8 bit number
Stores an 8 bit number
Positive edge triggeredPositive edge triggered
... but only when /EN is active LO... but only when /EN is active LO
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CLK
OEABCDEFGH
QAQBQCQDQEQFQGQH
374
111
3478
13141718
256912151619
74374 Octal D F/Fs with 3-State 74374 Octal D F/Fs with 3-State OutputsOutputs
Stores an 8 bit number
Stores an 8 bit number
Positive edge triggeredPositive edge triggered
/OE is active LO output enable
Determines when register contents are visible at the
outputs
/OE is active LO output enable
Determines when register contents are visible at the
outputs
Note: LW uses different labels from the 377, and from Katz!Note: LW uses different labels from the 377, and from Katz!
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670
Q4
D1
D4D3D2
Q3Q2Q1
GW
WAWB
GR
RARB
54
11
1413
12
15123
10976
Register FilesRegister Files
• You read or write one word at a time.
• 74670 4-by-4 Register File with 3-State Outputs
4 words of 4 bits each
Data in: D1,D2,D3,D4 Data out: Q1,Q2,Q3,Q4
Read selects: RB,RA Write selects: WB,WA
Active lowActive low read enable /GR, write enable /GW
Can read and write simultaneously.
No clock. Read or write when enables asserted.
Watch out for glitches!
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)
To write Word 1, set GW = 0 and (WB, WA) to (0,1)
To read Word 2, set GR = 0 and (RB, RA) to (1,0)
Store several wordsStore several words
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Random Access MemoriesRandom Access Memories
• Same idea as a register file, but optimized for very many words.
• Small RAM: 256 4-bit words.
• Larger RAM: 4 million 8-bit words.
• More details later.
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Shift RegistersShift Registers• Some registers are designed to change their
stored data.
• Shift registers shift their bits left or right.
For example, right shift:
Original contents 1000
Shift right: 0100
Shift again: 0010
…and again: 0001
… once more, wrapping: 1000
• Application: send a word to a modem bit-by-bit.
• We need some way to initialize the shift register.
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Input and OutputInput and Output• Serial inputSerial input
The shift register doesn’t wrap around from right to left.
Instead, the user provides the new leftmost bit.
• Parallel inputParallel input
You can specify the whole word at once.
• Serial outputSerial output
The bit just shifted off the right is visible at a pin.
• Parallel outputParallel output
Every stored bit is visible at an output pin.
This uses more pins, which can be a problem.
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S1
SL
S0 194
CLK
SR
QCQB QA
QDDCBA
CLR1
11
2
910
3456
7
15141312
74194 -more-74194 -more-4 bit bidirectional universal
shift register4 bit bidirectional universal
shift register
4 modes set by S1,S000: hold data (QA,QB,QC,QD)01: shift right (SR,QA,QB,QC)10: shift left (QB,QC,QD,SL)11: parallel load
4 modes set by S1,S000: hold data (QA,QB,QC,QD)01: shift right (SR,QA,QB,QC)10: shift left (QB,QC,QD,SL)11: parallel load
Positive edge triggeredPositive edge triggered
SL (aka LSI): left shift input
SR (aka RSI): right shift input
SL (aka LSI): left shift input
SR (aka RSI): right shift input
/CLR: asynchronous clear/CLR: asynchronous clear
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74194 continued74194 continued• Notation conflicts:
– LogicWorks uses SL, SR. Katz uses LSI, RSI.
– LW uses A,B,C,D for inputs and QA,QB,QC,QD for outputs.
– Motorola uses P0,P1,P2,P3 for inputs, Q0,Q1,Q2,Q3 for outputs and DSR & DSL for serial inputs.
• NoteNote that the normal LW convention is that A is the lo-order bit. This is the way you normally connect the hex keyboard and the hex display. For the 194, A and QA are the hi-order bits. It's confusing.
• Right shift in more detail. All together on the rising clock:
SR QA, QA QB, QB QC, QC QD, QD is lost.
Connecting QD to SR makes a circular shift register.
• Left shift in more detail.
SL QD, QD QC, QC QB, QB QA, QA is lost.
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Do Activity #2 NowDo Activity #2 NowTYPO: Question b, part 2, WB, WA = 11
Due: End of Class Today
RETAIN THE LAST PAGES (#3 & #4)!!
For Next Class:• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:– Sec 7.2, 7.3 of Katz
• This reading is necessary for getting points in the Studio Activity!