ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)
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ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)
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Transcript of ECE 301 – Digital Electronics Flip-Flops and Registers (Lecture #15)
ECE 301 – Digital Electronics
Flip-Flops and Registers
(Lecture #15)
ECE 301 - Digital Electronics 2
Basic Memory Elements
ECE 301 - Digital Electronics 3
Basic Memory Elements Basic Latch
A feedback connection of two NOR gates or two NAND gates, which can store one bit of information.
Can be set to 1 or reset to 0.
Gated Latch A basic latch that also includes input gating and a
control input signal (i.e. the clock).
Flip-Flop A storage element based on the gated latch principle,
which can have its output state changed only on the edge of the controlling clock signal.
ECE 301 - Digital Electronics 4
D Flip-Flop
ECE 301 - Digital Electronics 5
Master-Slave Flip-Flop
D Flip-Flop
ECE 301 - Digital Electronics 6
D Flip-Flop: Master-Slave
ECE 301 - Digital Electronics 7
D Flip-Flop: Master-Slave
D
Clock
Master active
Slave active
Y
Q
ECE 301 - Digital Electronics 8
Positive Edge-triggered Flip-Flop
D Flip-Flop
ECE 301 - Digital Electronics 9
D Flip-Flop: Edge-Triggered
positive edge
negative edge
ECE 301 - Digital Electronics 10
D Flip-Flop: Symbols
ECE 301 - Digital Electronics 11
D Flip-Flop: Function Table
ECE 301 - Digital Electronics 12
Comparison of Level-Sensitive and Edge-Triggered
Memory Elements
Basic Memory Elements
ECE 301 - Digital Electronics 13
D
Clock
Q a
Q b
D Q
Q
(b) Timing diagram
D Q
Q
D Q
Q
D
Clock Q a
Q b
Q c
Q c
Q b
Q a
(a) Circuit
Clk
Q c
Gated D Latch
Positive Edge-triggered D Flip-Flop
Negative Edge-triggered D Flip-Flop
+ Edge-triggered D FF
Gated D Latch
- Edge-triggered D FF
Note that the Latch, Positive Edge-triggered FF,
and Negative Edge-triggered FF each have a unique symbol
ECE 301 - Digital Electronics 14
Asynchronous Preset and Clear Signals
Flip-Flops
ECE 301 - Digital Electronics 15
Q
Q
D
Clock
(a) Circuit
D Q
Q
Preset
Clear
(b) Graphical symbol
Clear
Presetmaster slave
Asynchronous Preset and Clear
ECE 301 - Digital Electronics 16
JK Flip-Flop
Flip-Flops
ECE 301 - Digital Electronics 17
JK Flip-Flop
ECE 301 - Digital Electronics 18
JK Flip-Flop
ECE 301 - Digital Electronics 19
T Flip-Flop
Flip-Flops
ECE 301 - Digital Electronics 20
T Flip-Flop
ECE 301 - Digital Electronics 21
T Flip-Flop
ECE 301 - Digital Electronics 22
Registers
ECE 301 - Digital Electronics 23
Registers Register
Consists of N Flip-Flops Stores N bits Common clock used for all Flip-Flops
Shift Register A register that provides the ability to shift its
contents (either left or right). Must use Flip-Flops
Either edge-triggered or master-slave Cannot use Level-sensitive Gated Latches
ECE 301 - Digital Electronics 24
4-bit Register
Registers
ECE 301 - Digital Electronics 25
ECE 301 - Digital Electronics 26
4-bit Register with Parallel Load
Registers
ECE 301 - Digital Electronics 27
2-to-1 Multiplexer
ECE 301 - Digital Electronics 28
4-bit Serial-In Serial-OutShift Register
Registers
ECE 301 - Digital Electronics 29
4-bit SI/SO Shift Register
common clock Edge-triggeredFlip-Flop
ECE 301 - Digital Electronics 30
Parallel-In Parallel-OutShift Register
Registers
ECE 301 - Digital Electronics 31
Q 3 Q 2 Q 1 Q 0
ClockParallel input
Parallel output
Shift/LoadSerialinput
D Q
Q
D Q
Q
D Q
Q
D Q
Q2-to-1
Multiplexer
ECE 301 - Digital Electronics 32
Parallel-In Parallel-OutBi-directional Shift Register
Registers
ECE 301 - Digital Electronics 33
4-bit PI/PO Bi-directionalShift Register
ECE 301 - Digital Electronics 34
Acknowledgments
The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for
Digital Design (4th Edition).
They are the property of and are copyrighted by Pearson Education.
