Lab 10 - 1

Physics 120 Lab 10: Flip-flops and Registers

This set of laboratory exercises will require that you build s number of auxiliary circuits: 1 – A "debounced" switch. 2 – A comparator to turn a sine wave into a logic train. 3 – Two LED drivers as read-out devices. Set these up on one side of your board so that they are safe and readily available for use. 10.1 A primitive flip-flop: NAND Latch

This circuit, the most fundamental of flip-flop or memory circuits, can be built with either NANDs or NORs. We will build the NAND form:

Figure 10.1. A simple flip-flop: cross-coupled NAND latch

Build this latch and record its operation using three channels (S, R, and Q) and a

SCREENSHOT. Complete the logic table below and include it in the report.

Note which input combination defines the “memory state;” and make sure you

understand why the state is so called. 10.2 Watching Switch Bounce Bouncing of the contacts in a mechanical switch is hard to see because the bounces

do not occur at exactly repeatable times after the switch is pushed.

Figure 10.2: Switch bouncing at HIGH to LOW transition (pulled up through 10k)

 Lab 10 - 2

We can use the previous “R-S” flip-flop, with cross-coupled NAND gates, as a switch "debouncer". Add pull-up resistors and as input use a "bouncy" SPDT pushbutton. Ground its common terminal as shown below. Show that your circuit performs correctly by measuring from three channels, i.e., S (pin 1), R (pin 4), and Q (pin 3). Trigger the oscilloscope in the "Normal" mode (try a time-base of about 100 µs/cm to start) .You will need some patience and some fine adjustments of the trigger level. Show your results with a SCREENSHOT.

Why does the latch – a circuit designed to remember an input – work as a "debouncer"?

Figure 10.3. NAND latch as switch debouncer

Keep this circuit for the remainder of the exercises.

10.3 – D flip-flops

The simple R-S latch is instructive but rarely used in circuit design. A more complicated version, the clocked flip-flop, is much easier to work with.

The simplest of the clocked flip-flop types, the D, simply saves at its output (O) what is present at its input (D, for "data") just before the previous clocking edge. The particular D flip-flop used below, the 74HC74, responds to a rising edge of the clock input. Note that the ’74 DIP package includes two D flip-flops. Tie the inputs of the unused flip-flop high or low (this is just to keep the chip cool).

Dis-assert R (active low Reset) and S (active low Set, sometimes called Clear or Preset) by tying them high (as these are active LOW inputs) with 10 kΩ resistors to +5 V (pins 1, 2 & 4) to ease switching from HIGH to LOW. Ditto for the “D” input.

Clock the flip-flop with the “debounced” push button that you built.

 Lab 10 - 3

Figure 10.4. D flip-flop

• Confirm that the D flip-flop ignores information presented to its input (D) until the flip-

flop is clocked through input C (for "clock"). Demonstrate this with a SCREENSHOT (use a slow time-base and show C, D, and Q)

• Try asserting R . You can do this with a jumper wire; bounce is harmless here. Why? What happens if you try to clock in a HIGH at D while assertingR ?

• Try asserting R and S at the same time (something you would never purposely do in a useful circuit) with jumpers. What happens? (Look at both the Q and Q outputs) What determines what state the flip-flop rests in after you release both? (The answer provides a clue to why you would not want to assert both R and S in a circuit.)

10.4 A toggle – D flip-flop with feedback

The feedback in the circuit shown below may trouble you at first glance, as it appears that the circuit can oscillate. The clock, however, makes this circuit easy to analyze and, further, breaks the feedback path. Build the circuit and try it!

Figure 10.5. D flip-flop with inhibitory feedback

• First, clock the circuit manually using the "debounced" push-button. Document with a SCREENSHOT.

 Lab 10 - 4

The system clock is derived from the Audio frequency generator. Run a sine wave at a few Volts of amplitude into the comparator circuit (from lab 9) below. Check that the output is truly a train of logic pules and document with a SCREENSHOT.

Figure 10.6. Logic (0 to 5 V) clock from sine wave input

Keep this circuit for the remainder of the exercises.

• Next, clock the circuit with a square wave (0 to 5V), derived as above. Watch Clock and Q on the oscilloscope and document with a SCREENSHOT. What is the relation between fclock and the frequency of the output, fQUT?

• Increase the clock rate toward the function generator’s maximum and measure the flip-flop’s propagation delay. You will have to consider what IN (clock) and OUT levels to use when you measure the time elapsed (asking yourself just what it is that is “propagating.”) Document with a SCREENSHOT.

• At the high clock rate, measure the difference in the transition onset at Q versus Q . Document with a SCREENSHOT. Why might the transitions occur at different instances?

10.5 Shift register

This exercise requires two clocked inputs that vary from 0 V (LOW) to +5 V (HIGH). The system clock is derived from the audio generator, as above. A second clock serves as the INPUT and is derived from the function generator

A. Shift-register. This circuit delays the signal called “IN”, and synchronizes it to the clock.

Figure 10.7. Shift register

 Lab 10 - 5

With fclock (from the comparator square wave source) be at least 10-times fIN. (from the

function generator)., clock the circuit and use the function generator to provide “IN”.

• One flip-flop: Synchronizer – Use the scope to watch IN, and QA; trigger the scope on IN. Supply a SCREENSHOT (with QA, D, and C). – What accounts for the jitter in signal QA?

• Several flip-flops: Delay – Now watch a later output – QB, QC, or QD, along with IN; trigger the scope on IN. Supply SCREENSHOTs (with QA, D, C and each of QB, QC, or QD). – Note the effect of altering fclock.

B. "Double-Barreled" one-shot. A shift register plus NAND gates yield a "Double-Barreled" one-shot. Before we start, we will need a pair of read-out indicators.

Build two of the n-channel MOSFET LED drivers, shown below. These will be used to display the output from the D flip-flop register in the following exercise.

Fig. 10.8. N-channel MOSFET LED driver

Add NAND gates to the shift register circuit of figure 10.7, as shown below, and watch the two g outputs, along with TRIG, on the oscilloscope. Note the effect of altering fclock.

• Slow-motion check out: first use a "debounced" pushbutton to drive TRIG, and set the clock rate to one Hertz or less. Watch the one-shot outputs with oscilloscope probes and with the buffered LEDs. You should see first one LED then the other wink low, in response to this low-to-high transition.

• Full-speed check out: when you are satisfied that the circuit works, drive TRIG with a wave from your comparator circuit while clocking the device with a function generator (at a higher rate). Document with a SCREENSHOT.

 Lab 10 - 6

Figure 10.9. Digitally-timed (synchronous) one-shot (double-barreled)

To ensure you understand what this circuit is doing, draw a timing diagram (to be included with your report), showing TRIG, clock, the four flip-flop outputs, and the two outputs from the NAND gates.

What are the strengths and weaknesses of this circuit as a one-shot (pulse) circuit relative to an analog one-shot?