Sequential Circuits - Circuits Systems - Imperial College London
Sequential Circuits Part 2 - Duke Electrical and Computer...
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10/24/11 1 1 Sequential Circuit Design: Part 2 •C 2 MOS Latch • Two-phase clock generators • Four-phase clocking • Pipelining and NORA-CMOS • TSPC logic 3 C 2 MOS Logic • Goal: Make circuit operation independent of phase overlap • No need to worry about careful design of clock phases, clock inversions, etc • Really ingenious design!
Transcript of Sequential Circuits Part 2 - Duke Electrical and Computer...
10/24/11
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Sequential Circuit Design: Part 2
• C2MOS Latch
• Two-phase clock generators
• Four-phase clocking
• Pipelining and NORA-CMOS
• TSPC logic
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C2MOS Logic
• Goal: Make circuit operation independent of phase overlap
• No need to worry about careful design of clock phases, clock inversions, etc
• Really ingenious design!
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Flip-flop insensitive to clock overlap
VDDVDD
M1
M3
M4
M2 M6
M8
M7
M5
CL1 CL2
X
C2MOS master-slave negative edge-triggered D flip-flop
D
-section -section
Q
Modes of operation:1) Evaluate ( = 1) -section acts as inverter -section is in high-impedance (hold) mode2) Roles reversed for = 0
• Insensitive to clock overlap as long as clock rise and fall times are “small”
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C2MOS avoids Race ConditionsSignal propagation requires pull-up followed by pull-down, or vice versa
D
1
M1
M3
M2 M6
M7
M5
1
VDDVDD
(1-1) overlap
X
Only pull-down networks are enabled
Q D
VDDVDD
M1
M4
M2 M6
M8
M5
0 0
(0-0) overlap
X
Only pull-up networks are enabled
Q
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C2MOS avoids Race Conditions
Caution: If clock has low rise/fall times, then both pMOS and nMOS may conduct
Typically need rise/fall time at most five times clock propagation delay
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Pipelining
• Common in high-speed designs
• Combinational logic (stages) separated by registers
• Alternating clock phases typically used
• Race may occur if clock phases overlap
F G
Reg
iste
r
Reg
iste
r
1 2
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Pipelined Logic using C2MOS
InF Out
VDD VDD VDD
C2C1
GC3
NORA CMOS
What are the cons traints on F and G?
(NO RAce CMOS)
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Example
1
VDD VDDVDD
Number o f s tatic invers ions s hould be even
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NORA CMOS
• Targets implementation of fast, pipelined datapaths using dynamic logic
• Combines C2MOS pipeline registers and np-CMOS dynamic logic functional blocks– Combinational logic can be a mixture of static and dynamic logic
– Latch and logic (feeding latch) are clocked in such a way that both are simultaneously in either evaluation or hold (precharge)
– Block in evaluation during =1 is a -module, inverse is a -module
– -modules and -modules alternate
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NORA CMOS Modules
VDDVDD
PDNIn1In2In3
VDD
PUN Out
Combinational logic Latch
-module
VDD
Out
VDD
PDNIn1In2In3
VDD
In4
In4
VDD
-module
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NORA Logic Modules
Operation Modes
-block -block Logic Latch Logic Latch
= 0 Precharge Hold Evaluate Evaluate = 1 Evaluate Evaluate Precharge Hold
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Doubled C2MOS Latches
• Single clock (no inverse clock is needed)
• Requires redesign of C2MOS latch
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VDD VDD
Doubled n-C2MOS latch
VDD VDD
Doubled p-C2MOS latch
DQ
DQ
= 1, latch in transparent, evaluate mode = 0, latch in hold mode, only pull-up
network activeDual-stage approach: no races
Doubled C2MOS Latches
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Doubled C2MOS Latches: Advantages
• No even-inversion constraints between two latches, or between latch and a dynamic block
• Dynamic and static circuits can be mixed freely
• Logic functions can be included in the n-C2MOS or p-C2MOS latches, or placed between them
• Disadvantage: More transistors per latch (six, instead of four)
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TSPC - True Single Phase Clock Logic
VDD
Out
VDDVDD VDD
InStatic
Logic
PUN
PDN
Including logic into
the latch
Inserting logic between
latches
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Simplified TSPC Latch (Split-Output)
VDD VDD
DQ
A
-latch
VDD VDD
DQ
-latch• Reduced area• Voltage degradation at A
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Master-Slave Flip-flops
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Two-Phase Clock Generator
• Considerations:– Drive: added buffers
– Non-overlap: Two phases inverted with respect to each other
– Minimum skew
– Implement with NAND gates?
in1
2
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Registers with Load/Enable Inputs
C C C
C
Ld
Ld
1 2
D Q
Multiplexed input
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C C
C
Ld 1
2
D Q
Gated clockC
Enable
GndClock enablecircuit
Registers with Load/Enable Inputs
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Comments on Transmission Gates
(Common Misconceptions)
C
Enable
Gnd
Enabled
Clock enablecircuit
Transmission gate used here as an AND gate
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Ca
b
F = abTransmission gate is not an AND gate
Ca
b
F = a+b
Ca
b
Transmission gate network does notserve as an OR gate
Comments on Transmission Gates
(Common Misconceptions)
