Sequential Circuits II Document
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Transcript of Sequential Circuits II Document
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Digital DesignSequential Circuits II
(Finite State Machines revisited)March 14, 2002
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Finite State Machines Example: Edge Detector
Bit are received one at a time (one per cycle), such as: 000111010 time
Design a circuit that assertsits output for one cycle when the input bit stream changesfrom 0 to 1.
Try two different solutions.
FSM
CLK
IN OUT
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State Transition Diagram Solution A
ZEROOUT=0
CHANGEOUT=1
ONEOUT=0
IN=1
IN=1
IN=1 IN=0
IN=0
IN=0
IN PS NS OUT0 00 00 01 00 01 00 01 00 11 01 11 10 11 00 01 11 11 0
ZERO
CHANGE
ONE
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Solution A, circuit derivation
FF
FF
OUT
IN
NS1
NS0
PS1
PS0
IN PS NS OUT0 00 00 01 00 01 00 01 00 11 01 11 10 11 00 01 11 11 0
ZERO
CHANGE
ONE
00 01 11 100 0 0 0 -1 0 1 1 -
PS
IN
00 01 11 100 0 0 0 -1 1 1 1 -
PS
IN
00 01 11 100 0 1 0 -1 0 1 0 -
PS
IN
NS1= IN PS0
NS0= IN
OUT= PS1 PS0
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Solution BOutput depends non only on PS but also on input, IN
ZERO
ONE
IN=0OUT=0
IN=1OUT=1
IN=0OUT=0
IN=1OUT=0
FF
OUT
NS PSIN
IN PS NS OUT0 0 0 00 1 0 01 0 1 11 1 1 0
Let ZERO=0,ONE=1
NS = IN, OUT = IN PS
Whats the intuition about this solution?
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Edge detector timing diagrams
OUT (solution A)
IN
OUT (solution B)
CLK
Solution A: output follows the clock Solution B: output changes with input rising edge and is
asynchronous wrt the clock.
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FSM ComparisonSolution A
Moore Machine output function only of PS maybe more state synchronous outputs
no glitching one cycle delay full cycle of stable output
Solution BMealy Machine
output function of both PS & input maybe fewer states asynchronous outputs
if input glitches, so does output output immediately available output may not be stable long
enough to be useful:
CLK
IN
OUT CL
CLK
OUT
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FSM RecapMoore Machine Mealy Machine
STATE[output values]
input value
STATE
input value/output values
Both machine types allow one-hot implementations.
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FSM Optimization State Reduction:
Motivation:lower cost
fewer flip-flops in one-hot implementations
possibly fewer flip-flops in encoded implementations
more dont cares in NS logic
fewer gates in NS logicSimpler to design with extra states then reduce later.
Example: Odd parity checker.Two machines - identical behavior.
S0[0]
S1[1]
S2[0]
0
1
11
0
0
S0[0]
S1[1]
0
1
0
1
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State Reduction State Reduction is based on:Two states are equivalent if, for each
member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.
If two states are equivalent, one can be eliminated without effecting the behavior of the FSM.
Several algorithms exist: Row matching method. Implication table method.
Row Matching is based on the state-transition table:
If two states have the same output, and both transition to the same next state, or both transition to each other, or both self-loop, then they are equivalent.
Combine the equivalent states into a new renamed state.
Repeat until no more states are combined. Note: This algorithm is slightly
different than the book.
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Row Matching Example
NS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f g f 0 1g a f 0 1
State Transition Table
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Row Matching ExampleNS output
PS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e f 0 1e a f 0 1f e f 0 1
NS outputPS x=0 x=1 x=0 x=1a a b 0 0b c d 0 0c a d 0 0d e d 0 1e a d 0 1
Reduced State Transition Diagram
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State Reduction The row matching method is not guaranteed to result in
the optimal solution in all cases, because it only looks at pairs of states.
For example:
Another (more complicated) method guarantees the optimal solution:
Implication table method:See Mano, chapter 9.
S0
S1
S2
0/1
1/0
1/01/0
0/1
0/1
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State Assignment (from Katz) In encoded (non-one-hot) FSMs, the choice of binary
encodings for the states has an influence on the number of logic gates (or LUTs) needed to compute the next state and outputs.
For n states, at least s bits are needed for a binary encoding.
Where different encodings exist.
We will look at several by-hand heuristic methods for choosing good assignments.
Some CAD tools will make assignments automatically.
ns 2log=!2s
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State Maps
S0
S2
S3
S1
S4 00 01 11 100 S0 S4 S31 S1 S2
q1 q0q2 00 01 11 10
0 S0 S1 S3 S21 S4
q1 q0q2
AssignmentState q2 q1 q0
S0 0 0 0S1 1 0 1S2 1 1 1S3 0 1 0S4 0 1 1
AssignmentState q2 q1 q0
S0 0 0 0S1 0 0 1S2 0 1 0S3 0 1 1S4 1 1 1
K-maps are used to help visualize good encodings. Adjacent states in the STD should be made adjacent in the
map.
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State AssignmentAlternative heuristics based on input and output behavior as well
as transitions:
Adjacent assignments to:states that share a common next state(group 1's in next state map)
states that share a common ancestor state(group 1's in next state map)
states that have common output behavior(group 1's in output map)
Highest Priority
Medium Priority
Lowest Priority
i/j i/k
i/j i/j
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ExampleExample: 3-bit Sequence Detector
Highest Priority: (S3', S4')Medium Priority: (S3', S4')Lowest Priority:
0/0: (S0, S1', S3')1/0: (S0, S1', S3', S4')
Reset
S0
0,1/0
0,1/01/0
S1'0/0
0/1, 1/0
S3' S4'
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ExamplePaper and Pencil Methods
Reset State = 00
Highest Priority Adjacency
Not much difference in these two assignments
Not much difference in these two assignments
S0 S1
S3 S4
S0 S3
S1 S4
0 1
0
1
0
1
0 1
Q0
Q0
Q1
Q1
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State Assignment Example
Highest Priority: 2x(S1, S2)(S3', S4'), (S7', S10')
Medium Priority:(S1, S2), 2x(S3', S4'), (S7', S10')
Lowest Priority:0/0: (S0, S1, S2, S3', S4', S7')1/0: (S0, S1, S2, S3', S4', S7')
Another Example: 4 bit String Recognizer
Reset
S1
S3'
S7'
S2
S4'
S10'
0,1/0
0,1/0
0/0
0/0
1/0 1/0
1/0
1/0
1/00/1
S0
0/0
0/0
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State Assignment00 = Reset = S0
(S1, S2), (S3', S4'), (S7', S10')placed adjacently
State MapQ1 Q0
Q20
1
00 01 11 10
S0
Q1 Q0Q2
0
1
00 01 11 10
S0 S3'
S4'
Q1 Q0Q2
0
1
00 01 11 10
S0 S3'
S4'
S7'
S10'
Q1 Q0Q2
0
1
00 01 11 10
S0 S1 S3'
S2 S4'
S7'
S10'
Q1 Q0Q2
0
1
00 01 11 10
S0
Q1 Q0Q2
0
1
00 01 11 10
S0
S7' S10'
Q1 Q0Q2
0
1
00 01 11 10S0 S3'
S4'S7' S10'
Q1 Q0Q2
0
1
00 01 11 10
S0 S1 S3'
S2 S4'S7' S10'
(a) (b)
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State AssignmentEffect of Adjacencies on Next State Map
First encoding exhibits a better clustering of 1's in the next state map
Q 2 Q 1 Q 0 X
P 0
Q 2 Q 1 Q 0 X
P 0
Q 2 Q 1 Q 0 X
P 1 P 2
P 1
Q 2 Q 1 Q 0 X
Q 2 Q 1 Q 0 X
( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ' ) ( S 4 ' ) ( S 7 ' ) ( S ' 10 )
0
0
00
01
00 01 1 1 10
1 1
10
0
0
0
0
0
0 1
1 0
0
X
X
P 2
00
01
00 01 1 1 10
1 1
10
0
1
1
1
1
1
1
X
X
00
01
00 01 1 1 10
1 1
10
1
1
1
1
0
0
0
0
0
0
0
0
X
X
1
1
( S 0 ) ( S 1 ) ( S 2 ) ( S 3 ' ) ( S 4 ' ) ( S 7 ' ) ( S ' 10 )
000 001 101 01 1 1 1 1 010 1 10
X = 0 001 01 1 1 1 1 010 010 000 000
X = 1 101 1 1 1 01 1 010 1 10 000 000
Current State
Next State
000 001 010 01 1 100 101 1 10
X = 0 001 01 1 100 101 101 000 000
X = 1 010 100 01 1 101 1 10 000 000
Current State
Next State
1
1
0
0
1
1
0
0 0
0
1
Q 2 Q 1 Q 0 X
00
01
00 01 1 1 10
1 1
10
0
0
0
0
1
0 0
1 1
1
1
1
00
01
00 01 1 1 10
1 1
10
0
0
1
X
X
0
0
0
1
00
01
00 01 1 1 10
1 1
10
1
0
0
1
0
1
1
1
0
0
X
X
1
0
0
0
X
0
0
X
0
0
0
0 1