© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design...

© Digital Integrated Circuits2nd

Sequential Circuits

Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective

Designing SequentialDesigning SequentialLogic CircuitsLogic Circuits


Sequential Circuits

Naming ConventionsNaming Conventions

In our text: a latch is level sensitive a register is edge-triggered

There are many different naming conventions For instance, many books call edge-

triggered elements flip-flops This leads to confusion however


Sequential Circuits

Latch versus RegisterLatch versus Register Latch

stores data when clock is low

D

Clk

Q D

Clk

Q

Register

stores data when clock rises

Clk Clk

D D

Q Q


Sequential Circuits

Latch-Based DesignLatch-Based Design

• N latch is transparentwhen = 0

• P latch is transparent when = 1

NLatch

Logic

Logic

PLatch


Sequential Circuits

Timing DefinitionsTiming Definitions

t

CLK

t

D

tc 2 q

tholdtsu

t

Q DATASTABLE

DATASTABLE

Register

CLK

D Q


Sequential Circuits

Writing into a Static LatchWriting into a Static Latch

CLK

CLK

CLK

D

Q D

CLK

CLK

D

Converting into a MUXForcing the state(can implement as NMOS-only)

Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states


Sequential Circuits

Mux-Based LatchesMux-Based LatchesNegative latch(transparent when CLK= 0)

Positive latch(transparent when CLK= 1)

CLK

1

0D

Q 0

CLK

1D

Q

InClkQClkQ InClkQClkQ


Sequential Circuits

Edge-Triggered Flip-flopEdge-Triggered Flip-flop


Sequential Circuits

Static SR Flip-FlopStatic SR Flip-Flop

Writing data by pure forceNo clock needed (Asynchronous)

Clock version?


Sequential Circuits

Registers for PipeliningRegisters for Pipelining

+


Sequential Circuits

Registers for PipeliningRegisters for Pipelining

Pipelined

?


Sequential Circuits

SemiconductorSemiconductorMemoriesMemories


Sequential Circuits

MemoryMemory

Memory Classification Memory Architectures The Memory Core Periphery


Sequential Circuits

Semiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO


Sequential Circuits

Memory Timing: DefinitionsMemory Timing: Definitions

READ

WRITE

DATA

Read Access Read Access

Read Cycle

Data Valid

Data Written

Write Access

Write Cycle


Sequential Circuits

Memory Architecture: DecodersMemory Architecture: Decoders

Word 0

Word 1

Word 2

WordN22

WordN21

Storagecell

M bits M bits

S0

S1

S2

SN22

A0

A1

AK 21

K 5 log2N

SN21

Word 0

Word 1

Word 2

WordN22

WordN21

Storagecell

S0

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals:

N words == N select signals K = log2NDecoder reduces the number of select signals



Sequential Circuits

Array-Structured Memory ArchitectureArray-Structured Memory Architecture


Row

Dec

oder

AK

AK+1

AL-1

2L-K

Column Decoder

Bit Line

Word Line

A0

AK-1

Storage Cell

Sense Amplifiers / Drivers

M.2K

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Amplify swing torail-to-rail amplitude

Selects appropriateword


Sequential Circuits

Hierarchical Memory ArchitectureHierarchical Memory Architecture

Global Data Bus

RowAddress

ColumnAddress

BlockAddress

Block Selector GlobalAmplifier/Driver

I/O

Control

Circuitry

Advantages:1. Shorter wires within blocks2. Block address activates only 1 block => power savings


Sequential Circuits

Read-Only Memory Cells (ROM)Read-Only Memory Cells (ROM)

WL

BL

WL

BL

1WL

BL

WL

BL

WL

BL

0

VDD

WL

BL

GND

Diode ROM MOS ROM 1 MOS ROM 2


Sequential Circuits

MOS OR ROMMOS OR ROM

WL[0]

VDD

BL[0]

WL[1]

WL[2]

WL[3]

Vbias

BL[1]

Pull-down loads

BL[2] BL[3]

VDD


Sequential Circuits

MOS NOR ROMMOS NOR ROM

WL[0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Pull-up devices

BL [2] BL [3]

GND


Sequential Circuits

MOS NOR ROM LayoutMOS NOR ROM Layout

Programmming using theActive Layer Only

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion

Cell (9.5 x 7)


Sequential Circuits

MOS NAND ROMMOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL[3]BL [2]BL [1]BL [0]


Sequential Circuits

MOS NAND ROM LayoutMOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8 x 7)

Programmming usingthe Metal-1 Layer Only


Sequential Circuits

Precharged MOS NOR ROMPrecharged MOS NOR ROM

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.

WL [0]

GND

BL [0]

WL [1]

WL [2]

WL [3]

VDD

BL [1]

Precharge devices

BL [2] BL [3]

GND

pref


Sequential Circuits

Non-Volatile MemoriesNon-Volatile MemoriesThe Floating-gate transistor (FAMOS)The Floating-gate transistor (FAMOS)

Floating gate

Source

Substrate

Gate

Drain

n+ n+_p

tox

tox

Device cross-section Schematic symbol

G

S

D


Sequential Circuits

Floating-Gate Transistor ProgrammingFloating-Gate Transistor Programming

0 V

25 V 0 V

DS

Removing programming voltage leaves charge trapped

5 V

22.5 V 5 V

DS

Programming results in higher VT.

20 V

10 V 5 V 20 V

DS

Avalanche injection


Sequential Circuits

FLOTOX EEPROMFLOTOX EEPROM

Floating gate

Source

Substratep

Gate

Drain

n1 n1

FLOTOX transistorFowler-Nordheim I-V characteristic

20–30 nm

10 nm

-10 V

10 V

I

VGD


Sequential Circuits

EEPROM CellEEPROM Cell

WL

BL

VDD

Absolute threshold controlis hardUnprogrammed transistor might be depletion 2 transistor cell


Sequential Circuits

Flash EEPROMFlash EEPROM

Control gate

erasure

p-substrate

Floating gate

Thin tunneling oxide

n1source n1drainprogramming

Many other options …


Sequential Circuits

Cross-sections of NVM cellsCross-sections of NVM cells

EPROMFlashCourtesy Intel


Sequential Circuits

Characteristics of State-of-the-art NVMCharacteristics of State-of-the-art NVM


Sequential Circuits

Read-Write Memories (RAM)Read-Write Memories (RAM) STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended


Sequential Circuits

6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ


Sequential Circuits

CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)WL

BL

VDD

M 5

M 6

M 4

M1VDDVDD VDD

BL

Q = 1Q = 0

Cbit Cbit


Sequential Circuits

CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write)

BL = 1 BL = 0

Q = 0

Q = 1

M1

M4

M5

M6

VDD

VDD

WL


Sequential Circuits

6T-SRAM — Layout 6T-SRAM — Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6


Sequential Circuits

Resistance-load SRAM CellResistance-load SRAM Cell

Static power dissipation -- Want RL largeBit lines precharged to VDD to address tp problem

M3

RL RL

VDD

WL

Q Q

M1 M2

M4

BL BL


Sequential Circuits

SRAM CharacteristicsSRAM Characteristics


Sequential Circuits

3-Transistor DRAM Cell3-Transistor DRAM Cell

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn

WWL

BL1

M1 X

M3

M2

CS

BL2

RWL

VDD

VDD 2VT

DVVDD 2VTBL2

BL1

X

RWL

WWL


Sequential Circuits

3T-DRAM — Layout3T-DRAM — Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1


Sequential Circuits

1-Transistor DRAM Cell1-Transistor DRAM Cell

CSM1

BL

WL

CBL

WL

X

BL

VDD VT

VDD/2

VDD

GND

Write "1" Read "1"

sensingVDD/2

V VBL VPRE– VBIT VPRE– CS

CS CBL+------------------------= =

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.


Sequential Circuits

DRAM Cell ObservationsDRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD


Sequential Circuits

Sense Amp OperationSense Amp Operation

DV(1)

V(1)

V(0)

t

VPRE

VBL

Sense amp activatedWord line activated


Sequential Circuits

1-T DRAM Cell1-T DRAM CellM1 wordline

Diffusedbit line

Polysilicongate

Polysiliconplate

Capacitor

Cross-section Layout

Metal word line

Poly

SiO2

Field Oxiden+ n+

Inversion layerinduced byplate bias

Poly


Sequential Circuits

PeripheryPeriphery

Decoders Sense Amplifiers


Sequential Circuits

Row DecodersRow Decoders

Collection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


Sequential Circuits

Hierarchical DecodersHierarchical Decoders

• • •

• • •

A2A2

A 2A3

WL 0

A2A3A2A 3A2A3

A3 A3A 0A0

A0A 1A 0A1A0A1A0A1

A 1 A1

WL 1

Multi-stage implementation improves performance

NAND decoder usingNAND decoder using2-input pre-decoders2-input pre-decoders


Sequential Circuits

Dynamic DecodersDynamic Decoders

Precharge devices

VDD

GND

WL3

WL2

WL1

WL0

A0A0

GND

A1A1

WL3

A0A0 A1A1

WL 2

WL 1

WL 0

VDD

VDD

VDD

VDD

2-input NOR decoder 2-input NAND decoder


Sequential Circuits

4-input pass-transistor based column 4-input pass-transistor based column decoderdecoder

Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal pathDisadvantage: Large transistor count

A0S0

BL 0 BL 1 BL 2 BL 3

A1

S1

S2

S3

D


Sequential Circuits

4-to-1 tree based column decoder4-to-1 tree based column decoder

Number of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizingcombination of tree and pass transistor approaches

Solutions:

BL 0 BL 1 BL 2 BL 3

D

A 0

A 0

A1

A 1


Sequential Circuits

Sense AmplifiersSense Amplifiers

Idea: Use Sense Amplifer

outputinput

s.a.smalltransition


Sequential Circuits

Differential Sense AmplifierDifferential Sense Amplifier

Directly applicable toSRAMs

M4

M1

M5

M3

M2

VDD

bitbit

SE

Outy


Sequential Circuits

DRAM TimingDRAM Timing

© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design...

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