5 Chapter Synchronous Sequential Circuits 1. Logic Circuits- Review 2 Logic Circuits Sequential...
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5 Chapter Synchronous Sequential Circuits 1 Logic Circuits- Review 2 Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs an operation that can be specified by a set of Boolean functions. Employ storage elements in addition to logic gates. Outputs are a function of the inputs and the state of the storage elements. Output depend on present value of input + past input. Overview Storage Elements and Analysis Introduction to sequential circuits Types of sequential circuits Storage elements Latches Flip-flops Sequential circuit analysis State tables State diagrams 3 Introduction to Sequential Circuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops Combinatorial Logic: Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. 4 Combinational Logic Storage Elements Inputs Outputs State Next State Introduction to Sequential Circuits Sequential Logic Output function Outputs = g(Inputs, State) Next state function Next State = f(Inputs, State) 5 Combina- tional Logic Storage Elements Inputs Outputs State Next State Types of Sequential Circuits Depends on the times at which: storage elements observe their inputs, and storage elements change their state Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs at any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! 6 5.3 Storage Elements :Latches Storage elements Maintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit Switch states (0 1 or 1 0) when directed by an input signal Most basic storage element Used mainly to construct Flip-Flops Asynchronous storage circuit Types of latches: SR Latches S`R` Latches D Latches 7 X = X Basic (NOR) S R Latch Cross-coupling two NOR gates gives the S R Latch: 8 S (set) R (reset) Q Q Graphic Symbol R S Q Q Basic (NOR) S R Latch 9 Q t+1 Q t+1 QRS 1Q t+1 =Q = Undefined011 undefined111 Q t+1 RS Q t+1 =Q No change 00 Reset to 010 Set to 101 undefined11 Basic (NAND) Latch Cross-Coupling two NAND gates gives the - Latch: Q S (set) R (reset) Q 10 Graphic Symbol R Q Q S Basic (NAND) Latch 11 Q t+1 Q t+1 QRS ?? 000 ?? RS Undefined00 Reset to 110 Set to 001 Q t+1 =Q No change 11 Clocked S - R Latch Adding two NAND gates to the basic - NAND latch gives the clocked S R latch: Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high. C means control or clock. 12 S R Q C Q 1 1 S` R` D Latch(Transparent Latch) Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no indeterminate states! 13 C D Q Q D Q C Q D Latch(Transparent Latch) 14 Q D Q(t+1) Q t+1 D 00 11 Chapter 5: Sequential Circuits 5.4: Flip-Flops 15 Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Other flip-flops - JK flip-flop - T flip-flop 16 The Latch Timing Problem In a sequential circuit, paths may exist through combinational logic: From one storage element to another From a storage element back to the same storage element The combinational logic between a latch output and a latch input may be as simple as an interconnect For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1 17 The Latch Timing Problem (continued) Consider the following circuit: Suppose that initially Y = 0. As long as C = 1, the value of Y continues to change! The changes are based on the delay present on the loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock pulse 18 Clock Y C D Q Q Y The Latch Timing Problem (continued) A solution to the latch timing problem is to break the closed path from Y to Y within the storage element The commonly-used, path-breaking solutions replace the clocked D-latch with: a master-slave flip-flop an edge-triggered flip-flop 19 Master-Slave Flip-Flop Consists of two clocked D latches in series with the clock on the second latch inverted What happened when c=1? The data from D input is transferred to the master. The slave is disabled. Any change in the input change the master output ( Y ) but cant effect the slave output. 20 C D Q C C D Q D Master Slave Y What happened when C=0? The master is disabled. The slave is enable. The value of ( Y ) is transferred to the slave as input. The output ( Q ) is equal ( Y ). Conclusion: The output of the F.F. can change only during the transition of clock from 1 to 0 or at Trigger. 21 C D Q C C D Q D Master Slave Y Timing 22 A trigger: The state of a latch or flip-flop is switched by a change of the control input. 23 Timing Graphic Symbols 24 Graphic Symbols 25 Other flip-flops 26 Other F-Fs can be built using D F-F There are four operation on a F-F - set to 1 - Reset to 0 - toggle ( complement ) of Q - nothing There are tow F-F - JK F-F - T F-F JK Flip-Flops 27 JK Flip-Flops 28 D = JQ + KQ Q t+1 KJ No change Q t+1 = Q 00 Reset to 010 Set to 101 Complement Q t+1= Q 11 T Flip-Flops 29 T Flip-Flops 30 Characteristic Table 31 Characteristic Table 32 Characteristic Equations 33 34 State Equation 35 State Equation 36 37 38 Analysis This circuit consist of : 2 D F-F A and B Input x Output Y Q t+1 = D A= D A B = D B 39 40 41 State Table 42 43 State Diagram 44 45 state Input / output 46 47 1 D F-F ( A ) 2 Input X, Y Q t+1 = D D = A X y Analysis 48 49 50 51 2 JK F-F (A, B) Input x Q t+1 = JQ + KQ 52 Analysis 53 54 55 56 57 58 2 T F-F ( A, B ) 1 input X 1 output Y Q t+1 = T Q The input equations are T_A = BX T_B = X The out put equation is Y = AB The characteristic equations are : A t+1 = T_A A = BX A = BX(A) + (BX)A = ABX + AB + AX B t+1 = X B 59 Analysis 60 61