Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.
-
date post
20-Jan-2016 -
Category
Documents
-
view
228 -
download
0
Transcript of Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.
![Page 1: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/1.jpg)
Flip-Flops
Lecture L8.2
Section 7.1 – Book
Sect. 8.1– Handout
![Page 2: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/2.jpg)
Recall the !S-!R Latch
!S
!R
Q
!Q
0 00 11 01 1
!S !R Q !Q1
1
0
1 0 1
0 0 10 1 11 0 11 1 0
X Y nand
1 0 Set
1 0 Store
0 1 Reset
1 1 Disallowed
Q0 !Q0
![Page 3: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/3.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
0 1
1
1 0
1
![Page 4: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/4.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
1
0
1 0
1
1 0
1
![Page 5: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/5.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
1
0
1 0
1
0 1
1
![Page 6: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/6.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
1
0
0 1
1
0 1
0
![Page 7: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/7.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
1 1
0
0 1
0
0
1
![Page 8: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/8.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
1 1
0
1 1
0
0
1
![Page 9: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/9.jpg)
Edge-triggered D Flip-flop
!S
!R
Q
!Q
1
2
3
4
5
6
CLK
D
F1
F2
F3
F4
F5
F6
0 1
1
1 0
1
0
1
![Page 10: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/10.jpg)
D Flip-Flop
CLK
D Q
!Q0 0 11 1 0X 0 Q0 !Q0
D CLK Q !Q
D gets latched to Q on the rising edge of the clock.
Positive edge triggered
![Page 11: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/11.jpg)
Each Xilinx 95108 macrocell contains a D flip-flop
Controlled inverter
![Page 12: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/12.jpg)
Each Xilinx 95108 macrocell contains a D flip-flop
Note asynchronouspreset
x
Q.AP = x
Note asynchronousreset Q.AR = y
y
Q.D = z
z
![Page 13: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/13.jpg)
Divide-by-2 Counter
CLK
Q0
Q0.D = !Q0
CLK
D Q
!Q
Q0.D = !Q0
Q0Q0.D
!Q0
![Page 14: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/14.jpg)
MODULE div2cnt
TITLE 'Divide By 2 Counter'
DECLARATIONS
" INPUT PINS "
PB PIN 70; " push-button switch (clock)
" OUTPUT PINS "
Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16
div2cnt.abl
CLK
D Q
!Q
Q0.D = !Q0
Q0Q0.D
!Q0
RegisteredBuffer output
![Page 15: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/15.jpg)
EQUATIONS
Q0.C = PB;
Q0.D = !Q0;
test_vectors(PB -> Q0)
.C. -> 1;
.C. -> 0;
.C. -> 1;
.C. -> 0;
.C. -> 1;
.C. -> 0;
END
div2cnt.abl (cont’d)
CLK
D Q
!Q
Q0.D = !Q0
Q0Q0.D
!Q0
.C. means clock goesLO-HI-LO
Power-on output Q0 = 0
![Page 16: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/16.jpg)
A 1-Bit Register
CLK
D Q
!Q
CLK
Q0
!Q0
LOAD
INP0
Q0.D = Q0 & !LOAD # INP0 & LOAD
reg1Q0
!Q0
LOAD
INP0
CLK
![Page 17: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/17.jpg)
A 4-Bit Register
reg1Q0
!Q0
LOAD
INP0
reg1Q1
!Q1INP1
reg1Q2
!Q2INP2
reg1Q3
!Q3INP3
CLK
reg1Q0
!Q0
LOAD
INP0
CLK
![Page 18: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/18.jpg)
J-K Flip-flops
CLK
D Q
!Q
J
K
CLK
Q
!Q
Q.D = J & !Q # !K & Q
J K Eq. (8.1) 0 0 Q.D = Q 0 1 Q.D = 0 1 0 Q.D = !Q # Q = 1 1 1 Q.D = !Q
![Page 19: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/19.jpg)
J-K Flip-flops
J
CLK
Q
!QK
0 0 Q0 !Q00 1 0 11 0 1 01 1 TOGGLEX X 0 Q0 !Q0
J K CLK Q !Q
J K Eq. (8.1) 0 0 Q.D = Q 0 1 Q.D = 0 1 0 Q.D = !Q # Q = 1 1 1 Q.D = !Q
![Page 20: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/20.jpg)
T Eq. (8.2) 0 Q.D = Q 1 Q.D = !Q
T Flip-flops
CLK
D Q
!Q
CLK
Q
!QT
Q.D = T $ Q
![Page 21: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/21.jpg)
T Flip-flops
T
CLK
Q
!Q
0 Q !Q 1 !Q Q
T CLK Q !Q
T Eq. (8.2) 0 Q.D = Q 1 Q.D = !Q
![Page 22: Flip-Flops Lecture L8.2 Section 7.1 – Book Sect. 8.1– Handout.](https://reader036.fdocuments.us/reader036/viewer/2022062301/56649d6c5503460f94a4be0e/html5/thumbnails/22.jpg)
MODULE Tdiv2cntTITLE 'Divide By 2 Counter using T flip-flop' DECLARATIONS" INPUT PINS "PB PIN 70; " push-button switch (clock) " OUTPUT PINS "Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 EQUATIONSQ0.C = PB;Q0.T = 1; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END
T
CLK
Q
!Q
0 Q !Q 1 !Q Q
T CLK Q !Q1