EE201LIntroduction to Digital Circuits

Spring 2007Course Introduction

ByGandhi Puvvada

Practical Digital System Design

Breadboards and MSI components

Schematic entry and simulation CAD tools (ePD)

Xilinx FPGA boards

Lecture (1 Hour 20 min. per week)

Lab (2 Hour 40 min. per week)

Lec 30416R 42 38 0 02:00-03:20pm T Puvvada RTH115 Lec 30418R 35 19 0 03:30-04:50pm T Puvvada RTH115 Lec 30420R 35 13 0 10:30-11:50 W Puvvada RTH105

Lab 30422R Canceled 0 0 08:00-10:40 F

Lab 30424R 16 11 0 11:00-01:40pm T OHE336 Lab 30430R 16 7 0 11:00-01:40pm W OHE336 Lab 30428R 16 14 0 02:00-04:40pm Th OHE336 Lab 30432R 16 7 0 02:00-04:40pm F OHE336 Lab 30434R 16 14 0 06:00-08:40pm M OHE336 Lab 30436R 16 9 0 06:00-08:40pm W OHE336 Lab 30438R 16 8 0 06:00-08:40pm Th OHE336

Qz 30440R 180 51 0 04:00-06:00pm F TBA

Course Weights

Homeworks 10% Laboratory 35% Attendance mandatory Midterm Exam I 15% to 20% Midterm Exam II 30% to 25% Final Project 10%

BlackBoard

https://blackboard.usc.edu/https://totale.usc.edu/

Textbook

Digital Design: Principles and Practices, 4/EJohn F. Wakerly

Digilent Xilinx FPGA Board

Major TopicsBoard-level Design -- Basic Electrical aspects (Voltages & Currents)Combinational Logic Design Review -- Low-active signals, heuristic designState Machine Design -- EE101 method of Encoded State Assignment -- One-Hot State Assignment method -- Micro-programmed Control Unit methodDatapath Unit Design -- Data Registers with Data Enable

Small System Design

Homework Sample (HW#8 Q2) S <== smaller {P, Q} + smaller {X, Y}

Datapath

QI

Initial

QPQ

CompareP, Q

0~Reset

1

2QSPX

S <- P + X

On BUS #1

On BUS #2

Qxy2

CompareX, Y

On BUS #1

QXY1

CompareX, Y

QSPY

S <- P + Y

QSQX

S <- Q + X

QSQY

S <- Q + Y

3

4

56

7

START

11

1

1

START

On BUS #2

State diagram

Lab Sample: Coin dispenser

SW1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8LD

BTN1 2 3 BTN4

Anode ControlsA1A2A3A4

BA

BA BA BS

MSB

LSB0100101= 37c

ON

OFF

Quarters

DimesCents

uPC

Dow

n=St

op C

lock

BS

S1 S0 X_L

oa= SW3,6,8 Up

BTN1_main(Reset button)

Lab Sample: 7-bit Binary to 2-digit BCD converter

Initial

X<= Xin T<= 0

Done

Compare & Gather

if (X>=Ten) then X<= X-10102 T<= T+1

(X<Ten)

ACKSTART

RESET

ACKSTART

(X<Ten)

RTL Assignment operator“<=”

Relational operatorGreater than or Equal to

Subtractor Comparator

X-Register

10102

X_MUX_S1

X>=Ten

X_MUX_S0

I0I3 I1

Xin

I2

NC

10102

I0

I1

T_Inc

00002

I0

I1

T_Clr

T-R

egis

ter

IncrementerI+1

I

D Q

CLR

PRE

D Q

CLR

PRE

D Q

CLR

PRE

LD_MAIN BTN_MAIN

reset

SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8

Xin

6

Xin

5

Xin

4

Xin

3

Xin

2

Xin

1

Xin

0

A1 A2 A3 A4

Bin

ary

valu

e

BC

D v

alue

LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8

Q_I

Q_C

G

Q_D

ON

EBTN2 BTN4BTN3BTN1 BTN5

star

t

ack