EE201l Homework #8 · smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a...

ee201l_hw_8.fm

4/4/06 EE201L Homework #8 1 / 17 C Copyright 2006 Gandhi Puvvada

1. Datapath and control design: You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a complete data path. Notice that you can bring either P or Q on bus #1 (B_ONE) or bus #2 (B_TWO). SMALL_REG is only tied to B_ONE where as BIG_REG is only tied to B_TWO.

1.1 4-state state machine

1.1.1 Complete the state diagram below by writing state transition conditions.

1.1.2 Complete the one-hot implementation of the above 4-state state machine on page 3. Before you produce the outputs, answer the following questions.

1.1.2.1 Can we say that whenever we put P or Q on one of the two buses, we may put the other on the other bus? YES / NO

1.1.2.2 Can we say that, in the initial state, we may drive the buses even though it is not necessary? YES / NO

1.1.2.3 Can we say that we either load both SMALL_REG and BIG_REG or load none? YES / NO

1.1.3 Complete the waveform on page 4

IInitial

/RESET

START

STA

RT CPQ

Compare P with Q

on B_ONE on B_TWO

QPLLoad Q (from B_ONE) into Small.

1

1

Load P (from B_TWO) into BIG.

PQLLoad P (from B_ONE) into Small.Load Q (from B_TWO) into BIG.

EE201l Homework #8 Instructor: G. Puvvada

Datapath Design

ee201l_hw_8.fm


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ee201l_hw_8.fm


1.2 3-state state machine

1.2.1 The state machine design in 1.1 above is a ___________ (Mealy / Moore) as the outputs generated are not influenced by the inputs. The outputs are completely determined by the current state.

Let us now reduce the states by combining CPQ and PQL into CPQL ’compare and load’. The load operation is conditional in the CPQL state as can be seen below.

This 3-state state machine is a ___________ (Mealy / Moore).

Complete the state diagram below.

1.2.2 Complete the one-hot implementation of the 3-state state machine on page 6 .

1.2.3 Complete the waveform on page 7 .

IInitial

/RESET

START

STA

RT

QPLLoad Q (from B_ONE) into Small.

1

Load P (from B_TWO) into BIG.

CPQL

Load P (from B_ONE) into Small.Load Q (from B_TWO) into BIG.

Compare P (on B_ONE) with Q (on B_TWO).If appropriate

ee201l_hw_8.fm


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ee201l_hw_8.fm


2. Problem to solve: Add the smaller of P and Q to the smaller of X and Y and deposit the sum in the 4-bit register S.Though P, Q, X, and Y are all 3-bit unsigned numbers, we are using standard 4-bit TTL components in this design. The sum is a 4-bit sum. You do NOT need to refer to a TTL book.

S <== smaller {P, Q} + smaller {X, Y}

2.1 The DPU: The DPU (Data Path Unit on the next page) is nearly complete.Please analyze the same and answer the following questions.

2.1.1 Describe the function of the TTL chip 74LS244 briefly. Use terms such as two-state buffer, tristate buffer, inverting, non-inverting, active-low, active-high, quad / 4-bit wide, etc.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

2.1.2 Comparator connections and labels: Write VCC or GND in the boxes. Decide what you want to connect to the input pins A3 and B3 and show the same on page 9.

2.1.3 Adder connections: Decide what you want to connect to the input pins A4, B4 and C0 and to the output pin S4 and show the same on page.Note: A 4-bit sum is produced by adding two 3-bit items.

2.1.4 Register connections and labels: Write VCC or GND or S_LOAD or /S_LOAD or CLK in the two boxes. Decide what you want to connect to the input pin 4D and show the same on page 9.

2.1.5 Among P, Q, X and Y _____ and ____ can be led to any of the two buses whereas ____ can only go on to BUS #1 and ______ can only go on to Bus #2.

2.1.6 Describe the relation to be satisfied among the six control signals, /P2B1, /P2B2, /Q2B1, /Q2B2, /X2B1, and /Y2B2 so that there will not be any bus-contention. Describe the relation in words as well as in boolean equation form.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

ee201l_hw_8.fm


ee201l_hw_8.fm


2.1.7 Which of the following operations are feasible (to perform in one clock) using this data path? Circle the ones that are feasible and cross-out others.

Compare P and Q Compare X and Y

Compare P and X Compare Q and Y

S <-- P + Q S <-- P + X S <-- P + Y

S <-- Q + Q S <-- X + X S <-- Y

2.2 State diagram for the CU (Control Unit) to perform

S <-- smaller {P, Q} + smaller {X, Y}

Complete all missing transition conditions in the following state diagram. To arrive at the state transition conditions, consider whether it is appropriate to use actual signals such as FLS (or FLS) which are available in the datapath or whether it is appropriate to use fictitious signals (not available in the datapath) such as P>Q, X>Y, etc.

Notice the numbering of the states to facilitate possible implementation of the state machine using the microprogrammed control unit method. Is it ok if Mr. Bruin makes a mistake and swaps the numbers 2 and 5 for the states QXY1 and QXY2 ? OK / Not OK

QI

Initial

QPQ

CompareP, Q

0~Reset

1

2QSPX

S <- P + X

On BUS #1

On BUS #2

Qxy2

CompareX, Y

On BUS #1

QXY1

CompareX, Y

QSPY

S <- P + Y

QSQX

S <- Q + X

QSQY

S <- Q + Y

3

4

56

7

START

11

1

1

START

On BUS #2

ee201l_hw_8.fm


2.2.1 If P = Q and X = Y, which of the following sums gets deposited in S as per your state diagram? Circle the right one(s).

P + X P + Y Q + X Q + Y

2.3 Assuming that a ONE-HOT method is used for implementing this state machine, complete the output function table below and produce the 7 outputs using standard gates (AND, OR, NAND, NOR, INVERTER)

Output Function Table

2.4 Assuming that a microprogrammed CU method is used for implementing this state machine, arrive at the following design parameters:

Number of locations in the microprogram memory:Number of address pins on the microprogram memory:Size of the microprogram Counter:Size of the branch address field: Number of distinct branch conditions:Size of the condition select mux:Size of the condition select filed:

Size of the control signal (output control signal) field:

Total size of the micro-instruction: (putting together the condition select filed, the branch address field, and the control signal field)

Size of the microprogram memory needed:

OutputControl

Current State

/P2B

1

/P2B

2

/Q2B

1

/Q2B

2

/X2B

1

/Y2B

2

/S_L

OA

D

QI

QPQ

QXY1

QXY2

QSPX

QSPY

QSQX

QSQY

/P2B1

/P2B2

/Q2B1

/Q2B2

/X2B1

/Y2B2

/S_LOAD

ee201l_hw_8.fm


3. Design of a DPU (data path unit): This DPU needs to have a two 4-bit registers, A and B, and a 4-bit adder. The CU (control unit) sends to the DPU four signals as follows.

Signal Purpose

CLEAR To clear the registers A and B asynchronously

AS/BS Select A as the source or B as the source

AD/BD Select A as the destination or B as the destination

DO_IT Do the operation (add constant C to the selected source) and deposit theresult into the selected destination) (of course, do it at the clock edge)

The constant C comes from another unit. Here we are interested in only completing the DPU.

Complete the function table below

Operation SYS_CLK CLEAR DO_IT AS/BS AD/BD

Clear A, B X 0 X X X

No Change to A or B X 1 0 X X

A = A + C 1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

A B

ADDER

A[4:1]

S[4:1]

C

DPU

CO

NTR

OL

UN

IT

CU

CLEAR

AS/BS

AD/BD

DO_IT

SYS_CLK

4 4

4 4

4

B[4:1]

C0C4 GNDNC

ee201l_hw_8.fm


For storage elements: Use two 74LS173A registers for A and B.Processing element(s): Use a 74LS83A 4-bit binary adder for processing (adding in this case). Routing elements: Do you need any multiplexers or demultiplexers? Can you wisely make use of the tristate outputs of the two 74LS173A registers so as to avoid another mux chip?Think of bussing (forming a tristate bus of) the outputs of the two registers A and B and leading the bus to the input of the adders.

Make an effort to use the right symbols for the gates to make the schematic readable. Some of the gatingarrangements are given below. You may not need to use all of them!

7

74LS83A

A1

DO_ITAD / BD

DO_ITAD / BD

DO_ITAD / BD

DO_ITAD / BD

AS / BS

DO_IT

AS / BS

DO_IT DO_ITAD / BD

ee201l_hw_8.fm


4. Datapath, State Diagram, and Control Unit (one-hot) design

Serial vote counting: Inspect 8 votes (V0-V7) serially (one after another) through a mux. and find whether it is a DRAW (DRAW = TIE = equal number of YES and NO votes, i.e. four each). Here, we do not need any other inference such as Majority Vote, etc.

Partially complete state diagram is given later. Names of the states are:

I = INITIALC = COUNTINGDDT = DONE DRAW TRUEDDNT= DONE DRAW NOT TRUE

The datapath unit consists of mainly an 8-to-1 mux 74LS151 to select one vote at a time, three 74LS163A counters called S-Counter (to produce select lines for the 8-to-1 mux), Y-Counter (to keep track of the YES votes), and N-Counter (to keep track of the NO votes).

4.1 Complete the DPU (Data Path Unit) after completing the state diagram in the next part of this question. .

4.2

74x151ENABCD0D1D2D3D4

YY

711971032115

56

D5D6D7

141312

V

8-TO-1 MUX

74x163CLKCLRLDENPENTABCD

QAQBQCQD

RCO

2197103456

1413121115

N-COUNTER DPU

FOUR_N

FIVE_N


QAQBQCQD

RCO

2197103456

1413121115

Y-COUNTER

FOUR_Y

FIVE_Y


QAQBQCQD

RCO

2197103456

1413121115

S-COUNTER

LASTLAST_OVER

V0V1V2V3V4V5V6V7

ee201l_hw_8.fm


4.2.1 Complete the State diagram by finding the three conditions C1, C2, and C3.Write the conditions in the form of boolean expression below. Note: You should transit from COUNTING state to DONE DRAW NOT TRUE state as soon as possible (for example, if you find too many YES votes or too many NO votes). Hint: First figure out C3 and then express C1 and C2 in terms of C3.

C1 = ________________________________________

C2 = _________________________________________

C3 = __________________________________________

Hint for C3: Is it (FOUR_Y * V + FOUR_N * V)or is it (FIVE_Y + FIVE_N )?

4.2.2 For the three conditions C1, C2, C3 you figured out, check whether they satisfy the two properties, namely "ALL INCLUSIVITY” and “MUTUAL EXCLUSIVITY”. You can refer to pages 561/587 i n the 3rd edition of Wakerly (478/553 in the 2nd edition). Verify “ALL INCLUSIVITY”___________________________________________________

___________________________________________________________________________

Verify “MUTUAL EXCLUSIVITY”_____________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

___________________________________________________________________________

4.3 Design the control Unit using four D-FFs in a One-Hot method. Separately produce C1, C2, and

C

0~Reset

DDT

STA RTSTART I

DDNT

ACK

ACK

ACK

ACK

C1 = ?C2 = ?

C3 = ?

STATEDIAGRAM

Do NOT write C1, C2, and C3here as they may be longexpressions.

ee201l_hw_8.fm


C3 and use these (C1, C2, and C3) in the NSL (next state logic). Your design should include OFL (output function logic) to generate all necessary outputs to “control” the elements of the datapath unit. Also produce an output called DONE and an output called DRAW.

Q

QSET

CLR

D

QI

Q

QSET

CLR

DQC

Q

QSET

CLR

D

QDDT

Q

QSET

CLR

D

QDDNT

C3

C2

C1

Logic to produce C1, C2, C3

QI

QC

QDDT

QDDNT

V

EN_S_CTREN_Y_CTREN_N_CTR

/CLR_S_CTR/CLR_Y_CTR

/CLR_N_CTR

DONEDRAW

OFL

ee201l_hw_8.fm


4.4 Draw waveforms for a particular set of votes, namely V0 V1 V2 V3 V4 V5 V6 V7 = 0 1 0 0 1 0 0 1 No Yes No No Yes No No Yes .Do you spend eight clocks or less-than-eight clocks in the COUNTING state? ________________________________(all eight / less-than-eight).

Since there are more NO votes, hopefully, you have concluded that it is NOT a draw. Did you increment the S_COUNTER and N_COUNTER at the clock edge which led your state machine to go into the DDNT state. ________ (Yes, No) for the S_COUNTER; ________ (Yes, No) for the N_COUNTER

.

CLOCK

RESET

START

ACK

S_COUNT 000

V

QI

STATE I C

Y_COUNT

N_COUNT

Q C

QDDT

DONE

EN_S_CTR

EN_Y_CTR

EN_N_CTR

DRAW

QDONT

001 010 011

000 001

000 001

V 0 V1 V 2

EE201l Homework #8 · smaller in SMALL_REG and the bigger in BIG_REG. Given on the next page is a...

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