EE201L ClassNotes Ch9 · 2006-04-12 · EE201L_ClassNotes_Ch9.fm 4/12/06 EE201L Class Notes -...

EE201L_ClassNotes_Ch9.fm

4/12/06 EE201L Class Notes - Chapter #9 / 9C Copyright 2006 Gandhi Puvvada

Chapter 9Timing Design

(Based on Chapter 7 and Chapter 8 of Wakerly)

1 Metastability in bistables, latches, and flip-flops

• Bistable Question: How long the set or reset control should be active before becoming passive? Until the friendly echo arrives.

• D-LatchIf clock goes inactive immediately after D changes, the D latch can go into metastable state. See figure 7-12 (page 531) andfigure 7-14 (page 531) in Wakerly.

Q=0=>1

Q=1=>0

S = 1=>0=>1

R = 1

S

R

Q

Q

If this pulse is short,then Q,Q may go intoa metastable state



• D-FF (positive edge triggered)If clock goes high immediately after D changes, the master latch portion of the D-FF can go into metastable state. See figure 7-15 (page 532) and figure 7-17 (page 533) in Wakerly.

2 Why would D change around the clock

• Improper timing design

• Asynchronous inputs (push-button operation by a human)

• Due to clock Skew (clock may not reach all parts of the chip at the same exact time)

3 Setup time, Hold time, and Propagation delay of a Flip-FlopSetup time tsu: The D input shall be valid and stable for tsu time

before the significant edge of the clock.Hold time th: The D input shall be valid and stable for th time

after the significant edge of the clock.Note: There is only one value for tsu and th : the minimum.

There is no typical or maximum for these.After the clock edge, the Q output may change after a little time called propagation delay.

CLK

D[7:0]

tsu th



SN5474, SN54LS74A, SN54S74SN7474. SN74LS74A, SN74S74DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEARSDLS119 – DECEMBER 1983 – REVISED MARCH 1988

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

min

.on

ly



4 Timing Check, setup time margin and hold time margin

Please see figure 8-1 (page 682), figure 8-63 (page 760) and figure 8-64 (page 760) in Wakerly

Setup time Margin = tclk -tffPD(max) - tcomb(max) - tsetup(min) Hold time Margin = tffPD(min) + tcomb(min) - thold(min)

D QCLK

D QCLK

Next StateLogic

State MemoryQ0

Q1

Q0Q1

**

XD Q

CLK

D QCLK

IncrementerQ0

Q1

Q0Q1

**

ENCounterState machine

Reg

Reg R

egComb.Logic

Data PathA

BC

C <= A + B



What is hold time and why do we need it?Consider a shift register.

How do we fix hold time violation?

How do we fix setup time violation?

Where would you be concerned about the maximum delay path through the combinational logic?Where would you be concerned about the minimum delay path through the combinational logic?

D QCLK

D QCLK

D QCLK

D QCLK

D QCLK

Serial OutSerial In

CLK

Relation between tffpd th

Reg

Reg R

egComb.Logic



5 Asynchronous Inputs:

Examples of asynchronous inputs: Inputs from human, inputs from other subsystems working on a different independent clock

If the asynchronous input changes too late into the clock, the system can go into a wrong state!

Synchronization of asynchronous signals by using a synchronizing FF:

Simple intuitive answer: Well if it is the same edge we create a RACE condition. So it should be opposite edge. That is in fact a naive answer!A more thoughtful answer is that we use the same edge. Because of the finite propagation delay of the synchronizing FF (which is made sure to be greater than the hold time requirements of the receiving sys-tem/FFs), the RACE condition is carefully overcome in EVERY digital design.

Q1Q0 0 0

Q1Q0 1 0

Q1Q0 0 1

Q1Q0 1 1

X = 1X = 0

A

BC

D Wrong state reacheddue to X changingrather late.

D QCLK

D QCLK

Next StateLogic

State MemoryQ0

Q1

Q0Q1

**

XAsynchronous

D QCLK

D QCLK

Next StateLogic

State MemoryQ0

Q1

Q0Q1

**

XAX_Asynchronous D Q

CLK X_SynchronizedXS

Synchronizing flip-flopSample-and-hold flip-flop

Should this sampling edge bethe same or opposite of the significant edge of the system?



The clock for synchronization shall be the __________________________ (sending/receiving) sys-tem's clock. Example from EE201L homework #9:

Design # 1 experiences synchronization problems as the DO-IT signal is asynchronous to the (System-33/ System-44) and also the DONE signal is asynchronous to the (System-33/ System-44). Between Design #2 and # 3, is right and is wrong.

6 What is meant by flip-flops hardened against metastability?

It should be noted that even if a flip-flop goes into a metastable state, it is generally difficult for it to remain in such a state. It is like .... even if you manage to make a knife stand on its edge for a second, it is likely to fall one way or other very soon. By making the edge of the knife sharper, you reduce the prob-ability of its standing on its edge for notable length of time. Similarly, by increasing the loop gain of the cross connected pair of NAND gates/NOR gates making a bistable, any small disturbance (disturbance to the precarious metastable state) will get amplified and push the system to go into one of the two stable states of the bistable. Such flip-flops, which are made to very quickly come out of the metastable state even if they very rarely went in are called flip-flops hardened against metastability.

7 Double-synchronization helps to reduce the probability of failure due to metastability:

Syst

em b

ased

on

33 M

HZ

Clo

ck

Syst

em b

ased

on

44 M

HZ

Clo

ck

DO-IT

DONE

System-33 System-44

Design # 1

Syst

em b

ased

on

33 M

HZ

Clo

ck

Syst

em b

ased

on

44 M

HZ

Clo

ck

DO_IT

S_DONE

System-33 System-44

Design # 2

D QCLK

DQCLK

33 MHZ

44 MHZ

S_DO_IT

DONE

Syst

em b

ased

on

33 M

HZ

Clo

ck

Syst

em b

ased

on

44 M

HZ

Clo

ck

DO_IT

S_DONE

System-33 System-44

Design # 3

D QCLK

DQCLK

44 MHZ

S_DO_IT

DONE

33 MHZ

D QCLK

D QCLK

Next StateLogic

State MemoryQ0

Q1

Q0Q1

**

XAD Q

CLK

XSD Q

CLK

XSS

Here we employ two Synchronizing flip-flops.Even if the first one goes into a metastable state,it is expected that it would come out of the metastable state by the time the second flip-sloptries to sample the output of the first flip-flop.

Increases MTBF (Mean Time Between failures)

More in EE552/EE560: What do we do if we received a multi-bit asynchronous data? No, we do not use multiple synch. FFS.



8. Setup and hold time window shifts because of path delay in "D" or "CLK"

The setup and hold time of a D flip-flop are 0.3ns and 0.1ns, respectively; but because of the routing issues, some delay may occur on one or both input signals (CLK and D). The amount of this delay which can be modeled by a buffer is 0.04ns. In the presence of this delay, the setup and hold time of the whole circuit may change.

The setup and hold time of circuit A aretsetup= ; thold=

The setup and hold time of circuit B aretsetup= ; thold=

The setup and hold time of circuit C aretsetup= ; thold=

9 Result of severe clock-skew problem

D QCLK

tsetup= 0.3nsthold= 0.1ns

D QCLK

A

D QCLK

B

D QCLK

C

0.04ns

0.04ns

0.04ns

0.04ns

delay=0.04ns

D QCLK

Q Q

Q

D D

D

CLK

CLK CLK

Figures 8-65 (page 762) and 8-66 (page 763) from Wakerly.



10 Why does RES (asynchronous RESET) need to be synchronized to produce synchronous RESET?

Isn’t it true that if we are resetting the system anyway, we are aborting whatever we are doing and going into the INITIAL state. If so, does it matter if we abort synchronously or asynchronously?

It is not about when you go into reset. It is about when you come out of reset.

The RESET signal is usually generated using an R-C network. Hence it is an asynchronous signal. After the R-C time constant, if the reset signal becomes inactive just before (or at) the significant edge of the clock, then some flip-slops in the state memory may be able to come out of the reset state and start honoring the next-state bits standing at their D-inputs, while some other flip-flops may still be in the reset state. This causes the system to go into wrong/illegal states.

Let us first explain the problem using the 5-state dish-washer state-machine of EE201L. Let us assume that the ~RESET is asynchronous and becomes inactive just before (or at) the significant edge of the clock (positive edge in this problem). Also assume that the START happens to be true at that time. It is possible for the one-hot flip-flop QDONE to continue to remain in the reset state (QDONE = 1), while at the same time the QADD_WATER flip-flop may come out of reset and go to 1 (QADD_WATER = 1). So we have two FFs hot in the one-hot system! Solution: synchronize the asynchronous ~RESET to produce a synchronous reset signal ~SYNC_RESET

VCC

Reset PBRESET

A D DW A T E R R IN S E D R A IN D R Y D O N E

C S =

S T A R T = 1

D S = S T A R T = 0

D S =C S =

~ R E S E T

D QCLK

D QCLK

D QCLK

D QCLK

D QCLK

NSL

CS

NSL NSL

DSDS

QADD_WATER QRINSE

QDRAIN QDRY

QDONE

QDRAINCS

QDONE

START

START

RESET

D QCLK

RESET SYNC_RESET

Better to replace this with this.

CLK

RESET

QDONE

QADD_WATER

Too close to clock edge

EE201L ClassNotes Ch9 · 2006-04-12 · EE201L_ClassNotes_Ch9.fm 4/12/06 EE201L Class Notes -...

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