EE201L ClassNotes Ch3 - · EE201L_ClassNotes_Ch3.fm 2/13/07 EE201L Class Notes - Chapter #3 Page 2...

EE201L_ClassNotes_Ch3.fm

2/13/07 EE201L Class Notes - Chapter #3 / 18C Copyright 2007 Gandhi Puvvada

Chapter 3Combinational Logic Design

(Based on Chapter 6 Combinational Logic Design Practices in Wakerly)

1 Block Diagram and Schematic Diagram

In our course, we draw on paper logic diagrams and in ePD schematic diagrams.On paper drawings, we do not show IC numbers, pin numbers etc. We often provide functional names such as "3 to 8 decoder", "4-bit wide 2 to 1 mux", "8-bit register", etc. to the blocks in our logic diagram.

2 Signal Names and Active Levels

Home security Alarm: Assume that when a door is closed the switch attached to the door is also closed. Whenever a door is open (whenever a switch is open), we want a RED LED to glow.

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VCC

VCC RL

RL for RED LIGHT

VCC

VCC /RL

/RL for low-active RED LIGHT VCC

DO1

DO2

DO1

DO2

DO1 = DOOR 1 OPENDO2 = DORR 2 OPEN

RL = RED LED ON/RL = RED LED ONACTIVE HIGH

ACTIVE LOW



Another signal naming convention is READY# for a low-active ready signal.

Please differentiate between an operator and a char-acter which can be used in a signal name.The over-bar as in READY (pronounced as READY BAR, at least by me) and the accent mark (’) as in READY’ are operators and ideally should not be used as part of the signal name. This comes mainly from the CAD tool requirements. For example in a computer program, you can not name a variable "-A" because "-" is a subtraction operator. "-A" is an expression!However, because CAD tools came long after people started designing digital cir-cuits, signal names such as RD (for low-active READ) and WR (for low-active WRITE) are very common in industry, particularly in the microprocessor and peripheral area.

By default a signal is considered to be high active unless there is a special low-active indicator (such as "/", "~", "#", "*", or "_L") is used in the signal name.

Is every signal associated with an active level? No. Only signals which can be said to be active or inactive (asserted or deasserted) are associated with active levels.Usually such signals indicate an action (LOAD, CLEAR, RESET, ENABLE, INCREMENT, CHIP_SELECT, READ, WRITE, ACKNOWLEDGE, TAKE) or a status condition ( READY, BUSY, OVERFLOW, PARITY_ERROR, FULL, EMPTY, RECEIVED, etc.). However signals such as ADDRESS and DATA do not have active levels associ-ated with them. For the 8-bit data D[7:0], a value of 11111111 is not consider to be more active or significant compared to a value of 00000000. However, sometimes data bus is buffered by using inverting buffers at the exit of the mother board and again at the entry in every add-on card. Then it is common to use /D[7:0] as the signal name on the bus. Here the "/" is telling us that the data is inverted. It is NOT telling us that the data is active-low.

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Table 6.1 Wakerly



3 READABLE Logic Symbols

Draw "READABLE" logic. Use symbols which will prompt the reader to arrive at the same sentence that you had in your mind when you drew the logic.Example: Intent of the logic is that the global memory may be written only if (if and only if) the address belongs to the global memory and the processor indicates that it wants to write.The processor may have a high-active or a low active write output pin (WR or /WR).The global memory may have a high-active or a low active write input pin (WE or /WE).The address decoder designer may produce a high-active or a low active chip-select signal (GCS or /GCS) indicating that the address belongs to the global memory. Your job is to combine the two signals, write output from the processor and the chip-select signal from the address decoder, and produce a write-enable signal for the global memory. Complete the following four cases.

uPA[19:0]

WRA19A18A17A16

GCSWEGWE

GWEGCSWRGM

1 1 1

0 X

X 0

0

0

uPA[19:0]

/WRA19A18A17A16

/GCSWEGWE

GWE/GCS/WRGM

X

X

uPA[19:0]

/WRA19A18A17A16

/GCS/WE/GWE

/GWE/GCS/WRGM

X

X

uPA[19:0]

WRA19A18A17A16

GCS/WE/GWE

/GWEGCSWRGM

X

X


2/13/07 EE201L Class Notes - Chapter #3 Page 3 / 18C Copyright 2007 Gandhi Puvvada

3 READABLE Logic Symbols

Draw "READABLE" logic. Use symbols which will prompt the reader to arrive at the same sentence that you had in your mind when you drew the logic.Example: Intent of the logic is that the global memory may be written only if (if and only if) the address belongs to the global memory and the processor indicates that it wants to write.The processor may have a high-active or a low active write output pin (WR or /WR).The global memory may have a high-active or a low active write input pin (WE or /WE).The address decoder designer may produce a high-active or a low active chip-select signal (GCS or /GCS) indicating that the address belongs to the global memory. Your job is to combine the two signals, write output from the processor and the chip-select signal from the address decoder, and produce a write-enable signal for the global memory. Complete the following four cases.

uPA[19:0]

WRA19A18A17A16

GCSWEGWE

GWEGCSWRGM

1 1 1

0 X

X 0

0

0

uPA[19:0]

/WRA19A18A17A16

/GCSWEGWE

GWE/GCS/WRGM

X

X

uPA[19:0]

/WRA19A18A17A16

/GCS/WE/GWE

/GWE/GCS/WRGM

X

X

uPA[19:0]

WRA19A18A17A16

GCS/WE/GWE

/GWEGCSWRGM

X

X

SOLUTION



4 Exercising CONTROL

Often, in our designs, we exercise control such as the one we just saw.

the global memory may be written only if (if and only if) the address belongs to the global memory and ......

We notice that, depending on the situation, any one of the four gates can be used in exercising the control.

Examples of exercising control: -- Building larger decoders using smaller decoders by exploiting the enable

controls on the second level or subsequent level decoders. -- Building an 8-to-1 multiplexer using two 4-to-1 multiplexers by exploiting

the enable controls on the smaller multiplexers and making use of a gate to gather the outputs of the two smaller muxes into one at the output.

-- Building larger demultiplexers from smaller demultiplexers.

5 Examples showing READABLE symbols:

Memory shall write if System_0 says write or System_1 says write.Add bubbles to the gates as needed and complete the function tables.

Sys_

0 WR0

/WE/WE

Mem

X

X

WR0 WR1 /WE

Sys_

1 WR1

Sys_

0 WR0

WEWE

Mem

X

X

WR0 WR1 WE

Sys_

1 WR1

Sys_

0 /WR0

/WE/WE

Mem

X

X

/WR0 /WR1 /WE

Sys_

1 /WR1

Sys_

0 /WR0

WEWE

Mem

X

X

/WR0 /WR1 WE

Sys_

1 /WR1



4 Exercising CONTROL

Often, in our designs, we exercise control such as the one we just saw.

the global memory may be written only if (if and only if) the address belongs to the global memory and ......

We notice that, depending on the situation, any one of the four gates can be used in exercising the control.

Examples of exercising control: -- Building larger decoders using smaller decoders by exploiting the enable

controls on the second level or subsequent level decoders. -- Building an 8-to-1 multiplexer using two 4-to-1 multiplexers by exploiting

the enable controls on the smaller multiplexers and making use of a gate to gather the outputs of the two smaller muxes into one at the output.

-- Building larger demultiplexers from smaller demultiplexers.

5 Examples showing READABLE symbols:

Memory shall write if System_0 says write or System_1 says write.Add bubbles to the gates as needed and complete the function tables.

Sys_

0 WR0

/WE/WE

Mem

X

X

WR0 WR1 /WE

Sys_

1 WR1

Sys_

0 WR0

WEWE

Mem

X

X

WR0 WR1 WE

Sys_

1 WR1

Sys_

0 /WR0

/WE/WE

Mem

X

X

/WR0 /WR1 /WE

Sys_

1 /WR1

Sys_

0 /WR0

WEWE

Mem

X

X

/WR0 /WR1 WE

Sys_

1 /WR1

SOLUTION



Buffers: Buffers simply add more current drive capability so as to enable driving larger loads such as LEDs, long bus lines (ribbon cables, PCB traces going into add-on cards, etc. Two types of buffers and four symbols:

Non-inverting buffers: Note: Both symbols are identical.

Inverting buffers: Note: Both symbols are identical

Bubble-to-Bubble Logic Design (examples from Wakerly):

RD BRD

High-Active labels

/WR /BWR

Low-Active labels

RD /BRD

High-Active

/WR BWR

Low-ActiveLow-Active High-Active



6 Exercising Enable Control using a BARRIER gate:

The moment you add an enable control, you have to be concerned about two aspects.1. Is it active-high enable or active-low enable?2. When disabled, what value would I like to see as the disabled output?

Use one of the four 2-input gates (AND/OR/NOR/NAND) and optionally ONE inverter if needed to complete the following 8 cases of

enabling (allowing the input to have an affect on the output)and

disabling (disallowing the input to have an affect on the output).

YI

EN

Instead of simply viewing the output Y as equal to the productI . EN , let us view that Y is equal to I when enabled (when EN =1)else Y goes inactive meaning Y goes to "0".

Y = I . ENY = I if EN = 1, else Y = 0



In each of the following figures, add bubbles to the AND-shaped gate as needed. Use only standard gates. Use an inverter only if it is a must. Draw proper symbol for the inverter. You may have two choices to place the inverter.

Non-Inverting barrier control (Input, when allowed, reaches the output in its TRUE form):

Inverting barrier control (Input, when allowed, reaches the output in its COMPLEMENTED form):

7 A 2-to-1 Mux needs basically two barrier gates and a gathering gate.

The select line enables one of two barrier gates and disables the other.

The gathering gate will gather together the allowed value and the disabled output of the disabled gate into one final output.

YI

ENWhen disabled, Y =

/Y/I

/ENWhen disabled, /Y =

YI

/ENWhen disabled, Y =

/Y/I

ENWhen disabled, /Y =

/YI


Y/I


/YI


Y/I


YAI0

AI1

Allowed_I0

Allowed_I1

Final Y output

Gathering gate

Y = AI0 + AI1If I0 is allowed AI0 = I0.If I1 is disallowed, AI1 = 0Hence, Y is either AI0 or AI1.

Active-HighOne of them will be inactive



In each of the following figures, add bubbles to the AND-shaped gate as needed. Use only standard gates. Use an inverter only if it is a must. Draw proper symbol for the inverter. You may have two choices to place the inverter.

Non-Inverting barrier control (Input, when allowed, reaches the output in its TRUE form):

Inverting barrier control (Input, when allowed, reaches the output in its COMPLEMENTED form):

7 A 2-to-1 Mux needs basically two barrier gates and a gathering gate.

The select line enables one of two barrier gates and disables the other.

The gathering gate will gather together the allowed value and the disabled output of the disabled gate into one final output.

YI


/Y/I


YI


/Y/I


/YI


Y/I


/YI


Y/I


YAI0

AI1

Allowed_I0

Allowed_I1

Final Y output

Gathering gate

Y = AI0 + AI1If I0 is allowed AI0 = I0.If I1 is disallowed, AI1 = 0Hence, Y is either AI0 or AI1.

Active-HighOne of them will be inactive

SOLUTION



Insert bubbles as needed for each of the 4 gathering gate situations:

Given below are 4 non-inverting multiplexers making use of the four different gates as barrier gates. The first one is complete. Complete the rest of the three.Complete the select-line connections using one inverter. Use proper symbol for the inverter. Label the intermediate values as AI0 and AI1 or /AI0 and /AI1.Also add bubbles as needed for the gathering gate.

You know that by changing the output Y to /Y (or vice-versa) and adding or removing out-put bubble for the gathering gate, you can produce 4 inverting multiplexer designs.

Could you have done the same thing by changing bubbles elsewhere and adjusting the la-bels (without any further modification to the SELECT line and the inverter on it)? Mr. Bruin thinks that we have three more choices: change bubbles (1) at the input of the gathering gate (2) at the output of the barrier gates (3) at the input of the barrier gates. What do you say?

YAI0

AI1

Y/AI0

/AI1

/YAI0

AI1

/Y/AI0

/AI1

Y

AI0

AI1

I1

I0

S

/Y/I1

/I0

S

YI1

I0

S

/Y/I1

/I0

S

1 2

3 4



Insert bubbles as needed for each of the 4 gathering gate situations:

Given below are 4 non-inverting multiplexers making use of the four different gates as barrier gates. The first one is complete. Complete the rest of the three.Complete the select-line connections using one inverter. Use proper symbol for the inverter. Label the intermediate values as AI0 and AI1 or /AI0 and /AI1.Also add bubbles as needed for the gathering gate.

You know that by changing the output Y to /Y (or vice-versa) and adding or removing out-put bubble for the gathering gate, you can produce 4 inverting multiplexer designs.

Could you have done the same thing by changing bubbles elsewhere and adjusting the la-bels (without any further modification to the SELECT line and the inverter on it)? Mr. Bruin thinks that we have three more choices: change bubbles (1) at the input of the gathering gate (2) at the output of the barrier gates (3) at the input of the barrier gates. What do you say?

YAI0

AI1

Y/AI0

/AI1

/YAI0

AI1

/Y/AI0

/AI1

Y

AI0

AI1

I1

I0

S

/Y/I1

/I0

S

YI1

I0

S

/Y/I1

/I0

S

1 2

3 4

SOLUTION



Miss Bruin says, "Though the four non-inverting multiplexers are constructed us-ing different internal gates, they are all functionally identical. You can replace any one with anyone else. The muxes are identical very much like the following two non-inverters are identical."

Miss Bruin wants to transfer to USC. Would you recommend that we admit her?

Now consider adding an enable input to each of them. So assume that each barrier gate has 3 inputs as shown below. What kind of enable input (active-high EN or active-low /EN) can be added withoutrequiring any additional inverters?

Mr. Bruin is trying to copy Miss Bruins idea and is trying to get into USC. He says that the four designs after adding enables are still functionally identical. Do you agree or disagree? Or do you think that, not all the four but there are two pairs which are equal. Explain.

Y

AI0

AI1

I1

I0

S

/Y/I1

/I0

S

YI1

I0

S

/Y/I1

/I0

S

1 2

3 4

Active-high EN / Active-low /EN Active-high EN / Active-low /EN




Miss Bruin says, "Though the four non-inverting multiplexers are constructed us-ing different internal gates, they are all functionally identical. You can replace any one with anyone else. The muxes are identical very much like the following two non-inverters are identical."

Miss Bruin wants to transfer to USC. Would you recommend that we admit her?

Now consider adding an enable input to each of them. So assume that each barrier gate has 3 inputs as shown below. What kind of enable input (active-high EN or active-low /EN) can be added withoutrequiring any additional inverters?

Mr. Bruin is trying to copy Miss Bruins idea and is trying to get into USC. He says that the four designs after adding enables are still functionally identical. Do you agree or disagree? Or do you think that, not all the four but there are two pairs which are equal. Explain.

Y

AI0

AI1

I1

I0

S

/Y/I1

/I0

S

YI1

I0

S

/Y/I1

/I0

S

1 2

3 4



SOLUTION



8 Two labels for the same signal? problem with ePD

Sometimes you may like to name a signal in two different ways.

9 Confusing and non-uniform bubble convention Gate-level design vs. Block-level design

Consider the gate-level design of an inverting mux with active-low inputs /I0 and /I1, and active-high output Y. How should we encapsulate this design into a symbol?

/EN1/EN2

/ENABLE

DISABLE

Active-Low enableis

same asActive-High disable.

/EN1/EN2

/ENABLE

DISABLEDummy Buffer

ePD doesn’t allow two labels on the same net. So use a dummy buffer.

Y/I1

/I0

S /EN

Y/I0

/I1/EN S

Y I0

I1 EN S

Y/I0

/I1/EN S

No bubbles.Slashes in pin-names.

Bubbles.No slashes in pin-names.

Bubbles.Slashes in pin-names.

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Qua

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xer

E

E

SD



New IEEE symbol convention: Examples from TI datasheets:

Symbols used in ePD (and Xilinx Spartan2 library)

10 System labels and device labels (pin labels)

System labels are written outside the symbol on the nets (wires) where as device labels (pins labels) are written inside the symbol.

SD

From

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a D

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for

74LS

74A

Dua

l D-T

ype

Posi

tive

Edge

-Trig

gere

d Fl

ip-F

lop

74LS74A

74LS157

Triangleinstead of a circle

from tidip74LS library From Xilinx Spartan2 library

Y/I0

/I1/EN S

/WT_P0

/WT_P1

GM_WT

/WR_ENPROC_SEL



11 Matching active levels

Do not try to match active levels blindly. Understand the signal names and their meaning. In the design below, the nuclear reactor shall be made to wait until all sub-systems get ready. Complete the design using inverters as needed.

12 Exercise: 12.1 Does the following hook-up produce a 4-to-1 mux? If so, label it using 4E or /4E for the overall enable, 4I0, 4I1, 4I2, 4I3 or /4I0, /4I1, /4I2, /4I3 for inputs, 4Y or /4Y for the output and 4S1, 4S0 for the select lines.

12.2 Say, we do not need to the overall enable. Now try to use the enables on the left-side muxes to enable one mux at a time and replace the right-side mux with a suitable gathering gate.

/SS1R

/SS2R

/ASSRREACTOR

WAIT

Sub-System #1/RDY

Sub-System #1/RDY

Sub-system #1 Ready

All Sub-systems ReadySub-system #1 Ready

PIN LabelSystem Label

/Y/I1

/I0

S YI1

I0

S/Y

/I1

/I0

S

VCC



11 Matching active levels

Do not try to match active levels blindly. Understand the signal names and their meaning. In the design below, the nuclear reactor shall be made to wait until all sub-systems get ready. Complete the design using inverters as needed.

12 Exercise: 12.1 Does the following hook-up produce a 4-to-1 mux? If so, label it using 4E or /4E for the overall enable, 4I0, 4I1, 4I2, 4I3 or /4I0, /4I1, /4I2, /4I3 for inputs, 4Y or /4Y for the output and 4S1, 4S0 for the select lines.

12.2 Say, we do not need to the overall enable. Now try to use the enables on the left-side muxes to enable one mux at a time and replace the right-side mux with a suitable gathering gate.

/SS1R

/SS2R

/ASSRREACTOR

WAIT

Sub-System #1/RDY

Sub-System #1/RDY

Sub-system #1 Ready

All Sub-systems ReadySub-system #1 Ready

PIN LabelSystem Label

/Y/I1

/I0

S YI1

I0

S/Y

/I1

/I0

S

VCC

SOLUTION



13 Building larger muxes from smaller muxes (from EE101 notes and lab 4a)Method 1: Multiple levels or a tree of smaller muxes (similar to tournament brackets)

Method 2: Take advantage of an enable input

8S__ 8S__ 8S__

8YI1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

8I__

8I__

8I__

8I__

8I__

8I__

8I__

8I__8S0

8S1

8S2

8Y

I0I1I2I3S0S1

Y

4 to 1 mux8I48I58I68I7

I0I1I2I3S0S1

Y


I1

Y

S

I0

Selects OUT S2 S1 S0 Y 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1 1 0 I6 1 1 1 I7

Selects OUT S2 S1 S0 Y

0 I0 0 1 I1 0 I2 0 1 1 I3 0 I4 0 1 I5 0 I6 1 1 1 I7

Selects OUT S2 S1 S0 Y 0 1 0

0 1 1 0

0 1 0 0 1 1 1

8S0

8S1

8S2

8YI0I1I2I3S0S1

Y/E


I0I1I2I3S0S1

4 to 1 mux8I08I18I28I3 Y

/E

8S0

8S1

8S2

8YI0I1I2I3S0S1

/YE


I0I1I2I3S0S1

4 to 1 mux8I08I18I28I3 /Y

E

/8E



13 Building larger muxes from smaller muxes (from EE101 notes and lab 4a)Method 1: Multiple levels or a tree of smaller muxes (similar to tournament brackets)

Method 2: Take advantage of an enable input

8S__ 8S__ 8S__

8YI1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

8I__

8I__

8I__

8I__

8I__

8I__

8I__

8I__8S0

8S1

8S2

8Y

I0I1I2I3S0S1

Y


I0I1I2I3S0S1

Y


I1

Y

S

I0

Selects OUT S2 S1 S0 Y 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1 1 0 I6 1 1 1 I7

Selects OUT S2 S1 S0 Y

0 I0 0 1 I1 0 I2 0 1 1 I3 0 I4 0 1 I5 0 I6 1 1 1 I7

Selects OUT S2 S1 S0 Y 0 1 0

0 1 1 0

0 1 0 0 1 1 1

8S0

8S1

8S2

8YI0I1I2I3S0S1

Y/E


I0I1I2I3S0S1

4 to 1 mux8I08I18I28I3 Y

/E

8S0

8S1

8S2

8YI0I1I2I3S0S1

/YE


I0I1I2I3S0S1

4 to 1 mux8I08I18I28I3 /Y

E

/8E

SOLUTION



Name the following muxes:

/E S Output Y 1 X all 0’s 0 0 select A 0 1 select B

A1

A2

A3

A4

B1

B2

B3

B4

S

/E

Y1

Y2

Y3

Y4

74LS

157

S__ S__

Y

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0Y

S__

Y

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

Y

Y

Y

74L

S15174

LS1

53

74LS157

E A/B Y1 Y00

11

X01

A1 A0B1 B0

Function Table

Using as few inverters as possible,complete the design to suit thepartially complete function table.Then complete the function table.



Name the following muxes:

/E S Output Y 1 X all 0’s 0 0 select A 0 1 select B

A1

A2

A3

A4

B1

B2

B3

B4

S

/E

Y1

Y2

Y3

Y4

74LS

157

S__ S__

Y

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0Y

S__

Y

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

I1

Y

S

I0

Y

Y

Y

74L

S15174

LS1

53

74LS157

E A/B Y1 Y00

11

X01

A1 A0B1 B0

Function Table

Using as few inverters as possible,complete the design to suit thepartially complete function table.Then complete the function table.

SOLUTION



14 Binary Decoders; Building larger decoders from smaller decoders

B A

0 00 11 01 1

B

A/Y0 or Y0

/Y1 or Y1/Y2 or Y2

/Y3 or Y3/E or E

Function table for the 2-to-4 decoderSelect appropriate labels and complete the symbol and the function table.

A

B

Y0

Y1

Y2

Y3

AB

/E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

High-Active

Low

-Act

ive

Low

-Act

ive

If the following incomplete tree decoder has errors, report them. Otherwise complete it by labeling all inputs/outputs with suitable labels.

A

E1/E2

/Y0

/Y1

Build a 1-to-2 decoder with two enable inputs one active-low and another active-high, and active-low outputs as shown in the symbol.

Use two of these 1-to-2 decoders and two of 2-4 decoders to builda BCD decoder to decode B8 B4 B2 B1 to produce /DIG9 - /DIG0 to light-up the filaments of a Nixie Tube. Use as few inverters as possible.

A

E1/E2

/Y0

/Y1

AE1

/E2

/Y0

/Y1

AE1

/E2

/Y0

/Y1

/Y0

/Y1

/Y2

/Y3

AB

/E2

E1

/Y0

/Y1

/Y2

/Y3

AB

/E2

E1

/DIG

9

/DIG

8

/DIG

7/D

IG6

/DIG

5/D

IG4

/DIG

3/D

IG2

/DIG

1/D

IG0



14 Binary Decoders; Building larger decoders from smaller decoders

B A

0 00 11 01 1

B

A/Y0 or Y0

/Y1 or Y1/Y2 or Y2

/Y3 or Y3/E or E

Function table for the 2-to-4 decoderSelect appropriate labels and complete the symbol and the function table.

A

B

Y0

Y1

Y2

Y3

AB

/E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

/Y0

/Y1

/Y2

/Y3

AB

E

High-Active

Low

-Act

ive

Low

-Act

ive

If the following incomplete tree decoder has errors, report them. Otherwise complete it by labeling all inputs/outputs with suitable labels.

A

E1/E2

/Y0

/Y1

Build a 1-to-2 decoder with two enable inputs one active-low and another active-high, and active-low outputs as shown in the symbol.

Use two of these 1-to-2 decoders and two of 2-4 decoders to builda BCD decoder to decode B8 B4 B2 B1 to produce /DIG9 - /DIG0 to light-up the filaments of a Nixie Tube. Use as few inverters as possible.

A

E1/E2

/Y0

/Y1

AE1

/E2

/Y0

/Y1

AE1

/E2

/Y0

/Y1

/Y0

/Y1

/Y2

/Y3

AB

/E2

E1

/Y0

/Y1

/Y2

/Y3

AB

/E2

E1

/DIG

9

/DIG

8

/DIG

7/D

IG6

/DIG

5/D

IG4

/DIG

3/D

IG2

/DIG

1/D

IG0

SOLUTION



15 Demultiplexers: A demux delivers the input to a selected output. Non-inverting demuxes deliver the input to the selected output without inversion. Inverting demuxes deliver the input to the selected output with inversion The unselected output(s) will go to its/their disabled value. If there is an enable and if the enable is inactive, all outputs will go to their inactive (disabled) value irrespective of the input or the select line.

Exercise: Given below are two incomplete 1-to-2 demux designs and four choices for function tables to associate with these incomplete designs. (a) Complete the designs by labelling the input and outputs appropriately and select the associated function tables. State for each design, if it is an inverting demux or a non-inverting demux.Do you think you can possibly complete the designs in more than one way?(b) For the remaining two function tables, either provide suitable designs to go with or argue that those function tables are wrong.

Exercise: Complete the enable control addition to the demuxes below, label them, and complete the function tables.

INVERTING / NON-INVERTINGDisabled output gets a 0 / 1

/Y0 /Y1

0

S01

II0

/Y0 /Y1

1

S01

II1

0

S01

Y0 Y1/I

/I0

1

S01

Y0 Y1/I

/I1

S SINVERTING / NON-INVERTINGDisabled output gets a 0 / 1

S/E

S

01

/EX

S/E

S

01

/EX

not covered



Equivalence of a demux and a decoder with an enable input:

Exercise: Match items in Group A with items in Group B. Some items may not have a match.

Exercise: True or False?A demultiplexer can always be used as a decoder. T / FA decoder w/o (without) an enable cannot be used as a demultiplexer. T / F

Exercise: Describe each of the following demuxes as inverting/non-inverting with unselected outputs assuming a disabled value of 1 / 0 .

Exercise: In a microprocessor application, a low-active write control (/WR) shall be delivered to a chosen Global Memory (GM). The global memo-ries have high-active write input controls as shown.Which of the four demuxes above is/are suitable for this application (and why)?

/E

/y0

A

/y1

Decoder labels

S

/D

/D0

/D1

Demux labels

/y0

/y1

A

/E

/D0

S/D

/D1

1-to-2 decoder withactive low enable

input and active lowoutputs

1-to-2 non-invertingdemux with

unselected outputsassuming a 1

/E1

AX01

/y0

101

/y1

1100

S01

/D0

/D1

/D1

1/D

Group A Group B

3-to-8 Decoder w/ Enable 16-to-1 Multiplexer 8-to-1 Multiplexer 2-to-4 Decoder w/ Enable

1-to-4 Demultiplexer 1-to-8 Demultiplexer 16-to-1 Multiplexer 1-to-16 Demultiplexer

4-to-16 Decoder 2-to-4 Decoder w/o Enable

/I

Y0Y1Y2Y3

S0S1

/I

/Y0/Y1/Y2/Y3

S0S1

I

Y0Y1Y2Y3

S0S1

I

/Y0/Y1/Y2/Y3

S0S1

GMS1 GMS0

WE0WE1WE2WE3

GM0GM1GM2GM3

/WR

not covered



Demux with tristate buffers: Depending on the application, you may NOT want the unselected outputs to be floating. In that case, you can pull-up the unselected outputs to a default value of HIGH using pull-up resistances. Recall that only pull-up is pos-sible in bipolar TTL where as both pull-up and pull-down are possible in CMOS.

Label the inputs and output and complete the function table for the following demux.Also show how you would add an active-low enable input to it.

Complete the 1-to-4 demux below by making use of the 2-to-4 decoder in exercising the select control. Label the inputs and outputs. Discuss whether the resulting design can be used for the application shown on the right-side.

Vcc

10KOhm

Vcc

10KOhm

/E

S

S

0

1

Vcc

10KOhm

Vcc

10KOhm

S

S

01

/EX

Vcc

10KOhm

Vcc

10KOhm

Vcc

10KOhm

Vcc

10KOhm

A0

A1/Y1/Y2

/Y3

/Y0

GMS1 GMS0

WE0WE1WE2WE3

GM0GM1GM2GM3

/WR

not covered

EE201L ClassNotes Ch3 - · EE201L_ClassNotes_Ch3.fm 2/13/07 EE201L Class Notes - Chapter #3 Page 2...

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Transcript of EE201L ClassNotes Ch3 - · EE201L_ClassNotes_Ch3.fm 2/13/07 EE201L Class Notes - Chapter #3 Page 2...