1.1 WebPack Microsoft Windows Vista Business or Windows …...WebPack_MXE_Download_README_USC_r16.fm...

WebPack_MXE_Download_README_USC_r16.fm

January 25, 2008 10:26 pm Xilinx WebPACK Installation 1 / 15 C Copyright 2008 Gandhi Puvvada

Gandhi Puvvada

XILINX WebPack --Downloading and testing at USC (EE201L)

1 PC Operating system:

1.1 For the WebPack 9.2i release, the supported platforms are Microsoft Windows Vista Business or Windows XP Professional. During Xilinx software downloads, please disable (turn off) virus scanner and firewall to reduce installation time.

2 Download and save the test design files on your PC

2.1 Create the following directories:C:\xilinx_projects , C:\ModelSim_projects, and C:\Verilog The source verilog files and user constraint files (.v and .ucf) are held under C:\Verilog.

2.2 You are being given three zip files ( BIT_files.zip, verilog_s2.zip, and test_d2xldio1_verilog.zip).Download the zip files from the webpage specified on the BlackBoard into the directory C:\ on your PC. Extract BIT_files.zip in C:\ to form BIT_files subdirectory under C:\. Move the Verilog_s2.zip to C:\Verilog and extract to form C:\Verilog\Verilog_s2 and C:\Verilog\test_d2xldio1_verilog subdirectoris. Move the test_d2xldio1_verilog.zip from C:\ to C:\xilinx_projects and then extract to form C:\xilinx_projects\test_d2xldio1_verilog directory.

3 Installing WebPack, ChipScope Pro, and MXE

3.0 The following installation may take good 2 to 3 hours depending on the download speed of your internet connection. Currently the latest version of ISE WebPACK is 9.2i. Service Packs: As of 1/15/2008, service pack 4 is the latest service pack (the full version number is 9.2.04i). See http://www.xilinx.com/support/download/i92winsp.htm .As of 1/15/2008, the latest version of ModelSim Xilinx Edition is ModelSim XE III 6.2g.

3.1 Go to http://www.xilinx.com/. Click on Design Tools under Products and Services. This takes you to http://www.xilinx.com/products/design_resources/design_tool/index.htm . click on ISE™ WebPACK™ . This takes you to http://www.xilinx.com/ise/logic_design_prod/webpack.htm . Click on Download ISE WebPACK for Windows . This takes you to http://www.xilinx.com/support/download/i92winwp.htm. Exercise the following choices: 1. Select Download type: ISE WebPACK; 2. Select an ISE Version: 9.2i; 3. Select an OS: Windows. Click on . Actually, this search is not necessary as what we need is already displayed. Turn off virus scanner to reduce installation time. Click on either

or . If you are given a DVD, it will contain the full "single file". When click one of the above, it takes you to the xilinx login page. If this is your first download from xilinx web site, click on Create an account and setup your User ID and Password. Sign in using your User ID and Password. You do NOT need to note down the Product ID displayed. Click Next. Check-mark

the acknowledgement box and click Next.



3.1.1 The registration ID and the download link (http://www.xilinx.com/webpack/) gets sent to you by email. Click on Download ISE WebPACK .Create a folder called (say) Xilinx_Downloads on your desktop and save the zip file. It takes about 40 min. to an hour to download the 1.6GB zip file (WebPACK_SFD_92i.zip). (If your internet connection is bad, then only a few kilobytes of the 1.6GB zip file gets downloaded and you will receive an error when you try to unzip. Then you need try downloading again.) After downloading, unzip the file and run "setup.exe". If you do not have a unzip utility such as WinZip, you can download a free unzip/untar program called 7-zip from : www.7-zip.org

3.1.2• Click on setup.exe in the unzipped folder WebPACK_SFD_92i. Accept Software License agreement (3 parts).

• Destination Directory: Accept C:\Xilinx92i as the folder for destination directory for the xilinx software installation.Also accept the Xilinx ISE 9.2i as the Program Folder.

• Accept Use Internet Explorer Proxy Setting.

• Unselect/Select Xilinx Modules: Unselect: CPLD, Spartan3a, Virtex4, Virtex5Leave selected: Design Environment Tools Virtex/VirtexE/Spartan2/Spartan2 Virtex2/Virtex2P/Spartan3/Spartan3E Cable Drivers

This will require about 2.93 GBytes of yourdisk space.

• Leave the three items ticked. LMC_HOME, PATH, XILINX envi-ronment variables

• Select and begin in-stallation. Depending on the speed of yourcomputer, it can take more than an hour ??? (ifyou have a cable modem or DSL). It took 45minutes for me at my home. I am using Time Warner Cable. It is best to install it while you are on campus because of thehigher download rate. Do not attempt to install this if you have a dialup connection.

• Allow any over-writing of xilinx old drivers by xilinx new drivers as recommended by Xilinx.

• At the end of the installation, it shows an update request screen. click on .

• In the next screen you will click OK to download the service pack 3. As of 1/15/08, the latest ISE service pack is ISE 9.2i Service Pack 4 as shown



below . Click Ok.

It will take about 40 minutes to finish this update. At the end of this, you will be told to reboot. You can either reboot nowor choose to reboot later and let the "Update complete" and "Installation has completed" screens show up. Then rebootyour PC.

You will see the following icons on your desktop.

• Now that you finished all installation, after testing your installation, you can delete the following two temporary files/folders from your desktop/Xilinx_Downloads.

• Future updates: It is easy to get updates for ISE. When you invoke the ISE tool, go to Help ==> WebUpdate. If there areany updates, install the updates and check again to see that there are no more updates.

• If for any reason, you want to download an earlier version of the WebPACK, then please click on ISE Classics on the left panel of http://www.xilinx.com/ise/logic_design_prod/webpack.htm. This takes you to http://www.xilinx.com/ise/logic_design_prod/classics.htm.

3.1.3 Teaching Assistants: On the ISE tool, under Help, you find tutorials.You may also like to refer to the following tutorial if you have time.http://www.xilinx.com/support/software_manuals.htmhttp://www.xilinx.com/support/sw_manuals/xilinx92/index.htmAlso visit the tutorials page http://www.xilinx.com/support/techsup/tutorials .

Do not check the following option.

or



3.2 ChipScope Pro 9.2i installation (only installation, testing is covered separately):

• Go to http://www.xilinx.com/support/download/index.htm and make the three selections at the top.1. Select Download type: ChipScope Pro / ChipScope Pro Serial I/O Toolkit; 2. Select an ISE Version: 9.2i; 3. Selectan OS: Windows. Click on . In the next page, click on the left items (shown below) and down-load the right items shown below. You will have login each time.

• Double-click on the ChipScope_Pro_9_2i_win.exe file (downloaded a little before). It will perform self-extraction as shown be-low and show the welcome message.

• Click Next and you will be asked to enter the 16-digit registration ID. Enter the ID given to you. Note: This ID is given for USCstudents only. Please do NOT give it outsiders. Xilinx has been very generous to USC.

• Accept the license agreement.

• Destination Directory: Accept C:\Xilinx\ChipScope_Pro_9_2i as the folder for destination directory for the ChipScope soft-ware installation. Also accept the ChipScope Pro 9.2i as the Program Folder.

• Keep the two options selected.

• Begin Installation. Allow overwriting of any existing drivers from a previous installation.

• In a few minutes installation completes.

• ChipScope software update: You have downloaded earlier the file, ChipScope_Pro_9_2_04i_win.exe . Double-click on it.Accept the destination directory.

• Accept the update selection.

• In a few minutes update will be completed.

• Restart your computer before using the tool.

• Later when you use ChipScope, under its Help menu, you will find the ChipScope user guide. You can also access the same directly by doing Start => Programs => ChipScope Pro 9.2i => ChipScope Pro Software and CoresUser Guide (chipscope_pro_sw_9_2i_ug029.pdf)

14 MB

43.9MB



• I found the free webcast posted at the linkbelow very useful to get started with thetool.http://www.demosondemand.com/cli-ents/xilinx/001/page/index_destools.aspYou can register free and sign in andwatch the same

3.3 ModelSim XE III 6.2g starter limited version installation:

At http://www.xilinx.com/ise/mxe3/download.htm, click on mxe_3_6.2g.zip . Download the file to some temporary location.

• Right-click on the zip folder and extract files to mxe_3_6.2g folder.

• Click on setup.exe in the folder mxe_3_6.2g In the select compo-nents dialog box, select the second option, "MXE III Starter - Limited Version ofMXE III (Free)"Do not select the Full MXE III Edition as it is NOT free.

• Accept the license agreement.

• Destination Folder c:\Modeltech_xe_starter

• In the Library Installation Option The installer does not allow multiple libraries to be selected together; so select Full Verilog.

• Select Program Folder Accept the default: ModelSim XE III 6.2g . For a minute, nothing seems to be happening!

• After a few minutes of installation, Would you like a shortcut to Modelsim placed on your desktop? Yes Would you like ModelSim executable directory added to your path? Yes Complete the license request process following the setup? Yes Click on Finish in the ModelSim XE III Setup Complete dialog box.

• When the ModelSim Xilinx Edition License Request page appears,press ContinueIt asks you to enter your xilinx account User ID and Password. The license request form appears with your PC hard disc ID (VolumeSerial Number) as the HostID. You can verify this (if you want) using the command vol at DOSprompt. To get to DOS prompt, do START=>RUN=>cmd.You press submit on the form. Say OK in the next box. You willsee a confirmation message in a few seconds.The license file will be emailed to you in a few minutes. Sometimes it may take an hour or a day even!

• Extract the license file (license.dat) from your email (right click on the attachment and choose ’save target as’) to some



location, say c:\Verilog\MXE_license\. Make a copy of the file c:\Verilog\MXE_license\license.dat and paste it atC:\Modeltech_xe_starter\win32xoem\ .

• Invoke the Modelsim Licensing Wizard by (do not click on the Modelsim icon on the desktop) START => Programs => ModelSim XE III 6.2g => Licensing Wizardand follow directions. Browse and point the location of the license.dat file in win32xoem to the Licensing Wizard(C:\Modeltech_xe_starter\win32xoem\license.dat).

• Let the Licensing Wizard create LM_LICENSE_FILE variable asLM_LICENSE_FILE = C:\Modeltech_xe_starter\win32xoem\license.dat .

• Re-run the Licensing Wizard so that it goes through diagnostic tests and reports finding proper license.It says, "XE Starter simulator license (xe_starter) A perpetual license was found." and/or "The license checkout test hasbeen conducted successfully."

• Restart your computer so that the newly defined/redefined LM_LICENSE_FILE variable comes into ef-fect.

• Either now or at a later time (preferably now if you are not too tired), please setup the ModelSim simulatorfor VHDL also. To do that, again start by clicking on setup.exe in the Desk-top\Xilinx_Downloads\mxe_3_6.2g folder and repeat the above steps after that, this time choosing Full VHDL under Library Installation Option. ..... This time, .....

Would you like a shortcut to Modelsim placed on your desktop? No.Would you like ModelSim executable directory added to your path? No.Complete the license request process following the setup? No.Finish

• Go to http://www.xilinx.com/support/download/index.htm and make the three selections at the top.1. Select Download type: Modelsim XE Libraries; 2. Select an ISE Version: 9.2i; 3. Select an OS: Windows. Click on . In the next page, left-click on the left items (shown below) and download the zip files. You will have login.



• Now let us apply the update to ModelSim. Right-click on the zip folder and extract files to foldersmxe6.2g_9.2sp4_simulation_libraries and mxe6.2g_92i_ip2_xilinxcorelib. Inside the mxe6.2g_9.2sp4_simulation_libraries folder, you find a xilinx folder and a readme.txt file.Copy (or move) the xilinx folder from mxe6.2g_9.2sp4_simulation_libraries to C:\Modeltech_xe_starter directory. Windows will ask your permission (as shown in the side box) to replace files with identical names. Click "Yes to All". Some files get updated. After this, copy (or move) the xilinx folder from mxe6.2g_92i_ip2_xilinxcorelib to C:\Modeltech_xe_starter di-rectory. Windows will ask your permission (as in the previous case) to replace files with identical names. Click "Yes to All". Some files get updated.

• Now that you finished all installation, after testing your installation, you can delete all the files and folders brought into Desktop\Xilinx_Downloads\

3.3.1 For the TAs: Refer to the manuals, tutorials, and demos at the following pages, if you have time and if needed:http://www.model.com/resources/resources_manuals.asp , http://www.model.com/resources/resources_demos.asp .

4 Testing the WebPack and the Digilent D2XL+DIO1 board

4.1 Testing using Verilog HDL test design:

To hold your xilinx synthesis projects, you must have created a directory, called (say) C:\xilinx_projects under C:\ (or F:\xilinx_projects under F:\ if you plan to carry an USB memory stick with your project files so that you can work on your projects at home using your desktop PC as well as at school using the PCs in the labs. Then you can keep your source files in F:\Verilog and F\EDIF).

If you do not have patience to go through all the steps below to create a project and compile a test design, you can create the entire project directory by downloading test_d2xldio1_verilog.zip and unzipping it under the C:\xilinx_projects directory. In fact we asked you to do that at the beginning of this handout thinking that you get too tired by this time. If you are not tired, then rename the project directory previously created under C:\xilinx_projects and proceed.

4.1.1 Invoke webpack by clicking on the Xilinx ISE 9.2i icon. Or you can go through Start ==> Programs ==> Xilinx ISE 9.2i ==> Project Navigator.

4.1.2 Create a new project (click on File => New Project). In the New Project Wizard - Create New Project dialog box, first make sure that the project location is C:\xilinx_projects\ (or F:\xilinx_projects ). If you are working on our lab computers and if you are not using an USB memory stick, you may want to name the project with your short name as prefix, (for example, the student Mike would name it as Mike_test_d2xldio1_verilog) . Finally when you are done, you can remove the project directory C:\xilinx_projects\Mike_test_d2xldio1_verilog. Name the project test_d2xldio1_verilog (actually some arbitrary name).



4.1.3 The Device Properties dialog box comes up. Make sure the properties are selected as shown below.

4.1.4 Click Next in the create new source dialog box as we do NOT wish to create a new source file now.

4.1.5 In the Add Existing Sources dialog box, click on Add Source and point to the source file C:\Verilog\test_d2xldio1_verilog \test_d2xldio1_verilog.v. Click Add Source again and add the test_d2xldio1_verilog.ucf (.ucf = user constraint file) as a source file. Note: In this example, I am showing the "Copy to Project" checked. The advantage is that if you zip the project and take it to another computer, the project is self-contained with all the source files. The disadvantage is that if we update the source files in C:\Verilog, we need to remember to copy the latest files to the project directory. In any case, we like to keep the source file copies separately in C:\Verilog\<project_name> so that if we delete the project directory under C:\xilinx_projects, we do not lose the source files.

Pull-down



4.1.6 Project Summary appears. Click Finish.

4.1.7 Notice the association of files Synthesis/Implementation vs. Synthesis/Imp + Simulation. If you have a functional description of the core design, you usually will write a testbench. The test bench file should have file association with Simulation only. If needed, you need to use the pull-down menu to correct the file association.The .ucf file provides association of the FPGA pins to the input/output ports in our design.

4.1.8 Before you start synthesizing and/or implementing , it is important to select the TOP module (if it is not already selected (high-lighted)); otherwise you will be synthesizing a lower module! In this project, of course, there is only one module, test_d2xldio1_verilog.

4.1.9 Double-click on (or right-click and select Run on) Synthesize-XST.It may be a good practice to expand the Synthesize-XST and run Check Syntax for the first few times.

If the code is syntactically correct and is synthesizable, it will

Pull-down



synthesize. A green check-mark or an yellow warning sign is displayed.

Usually warnings can be ignored.

Now run "Implement Design". Again, you can ignore warnings.

4.1.10 Right click on Generate Programming File and right-click on Properties. (The next few lines are important as many students quite often forget to do this). In the Process Properties dialog box, choose the Startup options category. Select the FPGA Start-Up Clock as JTAG Clock. Click OK. Basically the FPGA boards (used in our courses) use a programing mechanism called Boundary Scan programming mechanism which uses JTAG clock. So we need to select the JTAG Clock as stated above.

4.1.11 Expand the Generate Programming File into three sub-operations. Double-click and complete the first step: i) Programming file Generation Report. You do not need to perform the step ii) Generate PROM file.We are not so much interested in the report produced in the above step (i) above. The .bit file is produced in that process. Check to see that test_d2xldio1_verilog.bit is generated in the c:\xilinx_projects\test_d2xldio1_verilog directory.

4.1.12 To configure the device (i.e. to download the .bit file into the FPGA), you need to have a parallel port on your PC. [If you only have a laptop with no parallel port, then you need to go to the OHE336 computers to program the FPGA.. Or borrow from your TA a special Digilent USB to JTAG programming cable and follow a separate guide provided for configuration using this Digilent cable.] Connect power-supply to the board. Make sure that the JTAG/PORT switch (black slide-switch) on the FPGA board is set to the JTAG side. Now you may click on the last option, "Configure Device (iMPACT).

4.1.13 Click Finish in the iMPACT window shown on the side.

4.1.14 Note: If you generated the bit file, test_d2xldio1_verilog.bit, on unix (or on the lap-top) and brought it to a PC with parallel port (say into C:\BIT_files directory), then you would invoke the iMPACT programming tool directly by clicking on the tool icon on the desktop

View the warnings by clicking on the "Warnings" tab of the bottom pane



(or Start => Xilinx ISE 9.2i => Accessories => iMPACT). Since the iMPACT tool does not find any

project directory it will ask you to create one. Create a project file test_d2xldio1_verilog.ipf under C:\BIT_files.

4.1.15 In the previous step the iMPACT tool identifies the device in the Boundary scan chain and displays the device (chip) as shown below on the left. The tool also opens up a "Assign New Configuration Dialog box shown in the right below. Click and select test_d2xldio1_verilog.bit. Then the bit file is shown below the chip as shown on the right. You can right-click on the chip and assign a different bit file if you wish.

4.1.16 Right-click on the chip symbol and select program. Initiate programming by clicking OK in the dialog box below. Leave the Verify unchecked.

4.1.17 The BTN1 on the mother-board is used for resetting our design. If you press any of the 5 buttons (BTN1 to BTN5) the walking LEDs pattern stops and the corresponding LEDs (LD1_LD2 for BTN1; LD3_LD4 for BTN2; LD5_LD6 for BTN3; LD7 for BTN4; and LD8 for BTN5; ) glow steadily. The binary equivalent of the 8-bit number set on the 8 switches SW1-SW8 is displayed in hex in its true and complemented form on the four 7-seg. displays. The single LED LD1 on the main board and the dot-points (DP) on the four 7-seg. displays keep flashing. The button on the main board acts like a RESET button.

4.1.18 Close the iMPACT window. You may choose not to save any file at this point, or if you save, then iMPACT



remembers next time that the bit file name. Close the main Project Navigator window also.

4.1.19 Now it is time to celebrate!!!!

5 Testing the ModelSim installation

5.1 Testing using a Verilog design and testbench

5.1.1 Create a directory, called (say) ModelSim_projects under C:\ (or under F:\) to hold the ModelSim simulation projects . Under this project create a folder called middle_finder to hold the project files for a small simulation project using the source files you imported into C:\VHDL\VHDL_s3.

5.1.2 Invoke ModelSimXE (Double-click the icon added to your desktop or go through Start ==> Programs ==> ModelSim XE III 6.2g ==> ModelSim).

5.1.2.1 In the welcome to ModelSim 6.2g dialog box click on

. Click on Create Project.

5.1.2.2 Choose suitable project location and project name.Type-in the project name as parity_gen (or something appropriate for your project), project location as C:/ModelSim_projects/parity_gen and Default Library Name as work (as chosen by the tool). Click OK. Note that we are naming our project as well as the folder holding the project files as parity_gen.

5.1.2.3 You will see the Add items to the Project dialog box . We suggest that you close this box. This box allows you to create a new hdl file or add an existing file. We suggest that you close this box.



5.1.2.4 We want you to use Project => Add to Project => Existing file. Keep the choice, ’Reference from current location’ selected. We do not want to have multiple copies of the source file(s).Browse and point to the two files: C:\Verilog\Verilog_D2\parity_gen.v. Click OK. Repeat the process for the test-bench C:\Verilog\Verilog_D2\parity_gen_tb.v

Note: When you create a project, a work directory is created under C:\ModelSim_projects\parity_gen . It contains a special file _info . You should not try to create this work directory by hand. You should let the tool (ModelSim) create it during the Create Project step.If you see the following warning, ignore it. They want to sell you their full product; you do not need anything more for this course!. Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.

5.1.3 Next time when you start ModelSimXE, in the welcome to ModelSim 6.2g dialog box click on OPEN PROJECT and choose the C:\ModelSim_projects\middle_finder. (Or you can opt to Proceed to ModelSim and do File => Open => Project). You can get back to the Welcome Window from the Help menu.

5.1.4 Before you compile, you need to make sure to tell the tool whether your code was written following Verilog 2001 syntax or the Verilog 1995 syntax. Select the parity_gen.v in the left panel of the ModelSim main window and right click and select properties. Project Compiler Settings dialog box opens up. Under the Verilog tab -- Make sure that the Use Verilog 2001 box is checked under Language Syntax .

5.1.4.1 Compilation: Several ways. Right click on the file and compile => compile selected ...Or from the Compile on menu bar... Or file open and compile.

5.1.4.2 Compile parity_gen.v. Modelsim will report an error in the transcript pane. Double-click red colored error-line to open detailed report with line numbers. You can right-click on parity_gen.v and select to edit. It opened the file. On inspecting the offending line 31, you notice that the variable "X" was typed in lower case "x".

Recall that Verilog is case-sensitive and "X" and "x" are different. Fix the error and recompile. This times it passes.



5.1.4.3 Compile the testbench (parity_gen_tb.v) also.The order of compilation shall be the innermost module is compiled first and then the one instantiating it is compiled next.

5.1.4.4 Yet another way of compiling is to use the vlog command (vcom for VHDL) at the ModelSim> prompt ModelSim> vlog C:/Verilog/Verilog_D2/parity_gen_tb.v Note the forward slashes in the above command. The back-slashes do not work (vlog C:\Verilog\Verilog_D2\parity_gen_tb.v does not work!)

5.1.5 Simulate => Start Simulation It opens the Start Simulation dialog box. With the Design tab active, expand work, and select parity_gen_tb and then click OK.

5.1.5.1 Notice that a new window called Objects is displaced with all the signals of the level of design currently active (testbench here). You can easily traverse through the hierarchy of the design and display signals in that level of hierarchy by simply clicking on the instance of a design in the left pane as shown below.

5.1.5.2 In the Objects window (while it is displaying the testbench signals), do Add => Wave => Signal in Region This adds the testbench signals to the waveform window.

5.1.5.3 Now you can further select the

in the Workspace pane on the left and select in the

Objects pane in the middle and add it to the wave pane on the right by right-clicking on test-count and selecting Add to Wave => Selected Signals.

5.1.5.4 In the Wave window, select the top signal by single left mouse click. Right_click and Select Format (in the wave window) => Radix => hexadecimalSimilarly, for the bottom-most item, select Format => Radix => decimal



5.1.5.5 Issue run command at the VSIM prompt: Use the zoom controls to inspect portions of the long waveform.

5.1.6 Please refer to modelsim commands available at http://www.model.com/resources/default.aspYou can register and receive a login password in an email from them. Then login.

Click on ModelSim under Product Demos. Further click on

Watch sections that interest you. Watch the and (about 8 minutes each).

5.1.7 Now it is time to celebrate!!!!

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