Chapter 6 Static CMOS Circuits Boonchuay Supmonchai Integrated Design Application Research (IDAR)...

Chapter 6Chapter 6

Static CMOS CircuitsStatic CMOS Circuits

Boonchuay SupmonchaiIntegrated Design Application Research (IDAR) Laboratory

August , 2004; Revised - June 28, 2005

2102-545 Digital ICs2102-545 Digital ICs Static CMOS Circuits 2

B.SupmonchaiB.Supmonchai

Goals of This ChapterGoals of This Chapter In-depth discussion of CMOS logic families

Static and DynamicStatic and Dynamic

Pass-TransistorPass-Transistor

Nonratioed and Ratioed LogicNonratioed and Ratioed Logic

Optimizing gate metrics Area, Speed, Energy or Robustness

High Performance circuit-design techniques



Combinational Combinational SequentialSequential

OutputOutput = = ff((InIn) )

CombinationalCombinationalLogicLogic

CircuitCircuitOutOutInIn

CombinationalCombinationalLogicLogic

CircuitCircuitOutOutInIn

StateState

OutputOutput = = ff((In, Previous InIn, Previous In) )

Combinational vs. Sequential LogicCombinational vs. Sequential Logic



Static CMOS CircuitsStatic CMOS Circuits At every point in time (except during the switching

transients) each gate output is connected to either each gate output is connected to either VVDDDD or V or VSSSS via a low-resistance path.

The outputs of the gates assume at all times the assume at all times the value of the Boolean functionvalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods)

This is in contrast to the dynamicdynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes



PUN and PDN are PUN and PDN are dualdual logic networks logic networks

F(InF(In11,In,In22,…In,…InNN))

VVDDDD

InIn11

PUNPUNPUNPUN

PDNPDNPDNPDN

InIn22

InInNN

……

InIn11

InIn22

InInNN

Static Complementary CMOSStatic Complementary CMOS

PMOS transistors onlyPMOS transistors only

NMOS transistors onlyNMOS transistors only

PPull-ull-UUp p NNetwork: make a connection etwork: make a connection from from VVDDDD to to FF when when F(InF(In11,In,In22,…In,…InNN)) = 1 = 1

PPull-ull-DDown own NNetwork: make a connection etwork: make a connection from from FF to GND when to GND when F(InF(In11,In,In22,…In,…InNN)) = 0 = 0



Threshold DropsThreshold Drops

PDNPDN

PUNPUN

CCLL

VVDDDD

VVDDDD

0 0

CCLL

VVDDDD

VVDDDD

VVDDDD

CCLL

0 0

VVDDDD

CCLL

SS

DD

SS

DD SS

DD

VVGSGS

SS

DD

VVGSGS

VVDDDD VVDDDD - - VVTnTn

00 |V|VTpTp||



AA

BBAA BB

Construction of PDNConstruction of PDN Transistors can be thought as a switch controlled by its

gate signal

NMOS switch closes when switch control input is high

NMOS Transistors pass a NMOS Transistors pass a “strong” 0“strong” 0 but a but a “weak” 1“weak” 1

A A • B• B

Series = NANDSeries = NAND

A A + B+ B

Parallel = NORParallel = NOR



Construction of PUNConstruction of PUN PMOS switch closes when switch control input is low.

PMOS Transistors pass a PMOS Transistors pass a “strong” 0“strong” 0 but a but a “weak” 1“weak” 1

AA

BBAA BB

Series = NORSeries = NOR

A A • B = • B = A A + + BB

Parallel = NANDParallel = NAND

A A + B = + B = A A • B • B



Duality of PUN and PDNDuality of PUN and PDN PUN and PDN are dual networks

De Morgan’s theorems

A parallelparallel connection of transistors in the PUN corresponds to a seriesseries connection of the PDN

Complementary gate is naturally invertinginverting (NAND, NOR, AOI, OAI)

Number of transistors for an NN-input logic gate is 2N2N

A + B = A A + B = A • B• B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A • B = A + BA • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]



A • BA • B

AA

BB

AA BB

AA BB FF

0 0 11

0 1 11

1 0 11

1 1 00

Example: CMOS NAND gateExample: CMOS NAND gate

VVDDDD

AA

BBFF

PDN: G = A · BPDN: G = A · B

PUN: F = A + BPUN: F = A + B

Conduction to GNDConduction to GND

Conduction to VConduction to VDDDD

GG((InIn11, , InIn22, …, , …, InInNN) = ) = FF((InIn11, , InIn22, …, , …, InInNN) )



Example: CMOS NOR gateExample: CMOS NOR gate

A + BA + B

AA

BB

AA BB

VVDDDD AA BB FF

0 0 11

0 1 00

1 0 00

1 1 00

AABB

FF



DD

AA

BB CC

DD

AA

BB

CC

OUT = D + A • (B + C)OUT = D + A • (B + C)

Complex CMOS GateComplex CMOS Gate

Derive PUN hierarchicallyDerive PUN hierarchicallyby identifying sub-netsby identifying sub-nets



Cell Design: An IntroductionCell Design: An Introduction Standard CellsStandard Cells

A general purpose logic

Synthesizable

Same height but varying width

Datapath CellsDatapath Cells For regular, structured designs (arithmetic)

Including some wiring in the cell

Fixed height and width



Example of A Standard CellExample of A Standard Cell

Cell boundary

N Well

Cell height 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objects

2

Rails ~10

InOut

VDD

GND

Cell height is “12 pitch”

Minimum-SizeMinimum-SizeInverterInverter



signals

Routing channel

VDD

GND

Standard Cell Layout MethodologyStandard Cell Layout Methodology – 1980s– 1980s

Routing channel What logic function is this?What logic function is this?



M2M2

No Routingchannels

VDD

GNDM3M3

VDD

GND

Mirrored Cell

Mirrored Cell

Standard Cell Layout Methodology – 1990sStandard Cell Layout Methodology – 1990s



Contains no dimensionsRepresents relative positions of transistors

InverterInverter

In

Out

VDD

GND

NAND2NAND2

A

Out

VDD

GNDB

Stick DiagramsStick Diagrams



OAI21 Logic GraphOAI21 Logic Graph

CC

AA BB

BB

AACC

ii

jj

jj

VDDX

X

ii

GND

AB

CPUNPUN

PDNPDN

AABBCC

X = C • (A + B)X = C • (A + B)

Node of thecircuit

TransitionControl



Two Stick Diagrams of Two Stick Diagrams of C C •• (A + B) (A + B)

A B C

X

VDD

GND

X

CA B

VDD

GND

Crossover can be eliminated by re-ordering inputsCrossover can be eliminated by re-ordering inputs



jj

VDDX

X

ii

GND

AB

C

AA BB CC

For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)

Consistent Euler PathConsistent Euler Path An uninterrupted diffusion strip is possible only if there

exists an Euler path in the logic graph

Euler pathEuler path:: a path through all nodes in the graph such that each edge is visited once and only once.



AABBCCDD

CC

AA BB

BB

AA

DD

CC

DD

X = (A+B)•(C+D)X = (A+B)•(C+D)VDDX

X

GND

AB

C

PUNPUN

PDNPDN

D

OAI22 Logic GraphOAI22 Logic Graph



BA D

VDD

GND

C

X

Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)

OAI22 LayoutOAI22 Layout



AA

BBA A B B

XNORXNOR XORXOR

AA

BB

A A B B A A B BAA

BB

AA

BBA A B B

How many transistor in each?How many transistor in each? Can you create the stick diagrams for the lower left circuit?Can you create the stick diagrams for the lower left circuit?

XNOR/XOR ImplementationXNOR/XOR Implementation



VVGS2GS2 = V = VA A –V–VDS1DS1

VVGS1GS1 = V = VBB

M1

M2

M3 M4

AA

BB

F= A • BF= A • B

AA BB

CCintint

D

DS

S 0

1

2

3

0 1 2

A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->1

0.50.5/0.25/0.25 NMOS NMOS0.750.75 /0.25 /0.25 PMOS PMOS

weakerweakerPUNPUN

VTC Characteristics are dependent upon the VTC Characteristics are dependent upon the data input patterns data input patterns applied to the gateapplied to the gate (so (so the noise margins are also data dependentthe noise margins are also data dependent!)!)

VTC is Data-DependentVTC is Data-Dependent



Observation IObservation I The difference between the blueblue and the orangeorange

lines results from the state of internal node int between the two NMOS Devices.

The threshold voltage of M2 is higher than M1 due to the body effect (), VSB of M2 is not zero (when VB = 0) due to the

presence of Cint

VVTn1Tn1 = = VVTn0Tn0 and and V VTn2Tn2 = = VVTn0Tn0 + + (((|2(|2FF| + | + VVintint) - ) - |2|2FF|)|)



Review: CMOS Inverter - DynamicReview: CMOS Inverter - Dynamic

tpHL = f(Rn, CL)

tpHL = 0.69 Reqn CL

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.52 CL / (W/Ln k’n VDSATn )

VVDDDD

RRnn

VVoutout

VVin in = V= V DD DD

CCLL

propagation delay is determined by the time to propagation delay is determined by the time to charge and discharge the load capacitor charge and discharge the load capacitor CCLL



Review: Designing for PerformanceReview: Designing for Performance Reduce CReduce CLL

Increase W/L ratio of the transistorIncrease W/L ratio of the transistor the most powerful and effective performance optimization tool

watch out for self-loading!

Increase VIncrease VDDDD

only minimal improvement in performance at the cost of increased energy dissipation

Slope engineeringSlope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values good for performance and power consumption



AA

RReqeqAA

CCLL

AA

RRnn

AA

RRpp

BB

RRpp

BB

RRnn CCintint

NANDNAND

RRpp

AA

AA

RRnn CCLL

INVERTERINVERTER

RRpp

RRpp

RRnn RRnn CCLL

CCintint

BB

AA

AA BB

NORNOR

Switch Delay ModelSwitch Delay Model



Input Pattern Effects on DelayInput Pattern Effects on Delay Delay is dependent on the patternpattern of inputs

Low to high transitionLow to high transition

both inputs go low delay is 0.69 0.69 RRpp/2/2 CCLL since two p-resistors are

on in parallel

one input goes low delay is 0.69 0.69 RRpp C CLL

High to low transitionHigh to low transition

both inputs go high delay is 0.690.69 22RRnn C CLL

Adding transistors in series (without sizing) slows down the circuit

CCLL

AA

RRnn

AA

RRpp

BB

RRpp

BB

RRnn CCintint

NANDNAND



Delay Dependence on Input PatternsDelay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=10

A=1, B=10

A=1 0, B=1

time [ps]time [ps]

Vo

ltag

e [V

]V

olt

age

[V]

Input DataInput Data

PatternPattern

DelayDelay

(psec)(psec)

A=B=01 67

A=1, B=01 64

A= 01, B=1 61

A=B=1A=B=100 4545

A=1, B=1A=1, B=100 8080

A= 1A= 10, B=10, B=1 8181

NMOS = 0.5NMOS = 0.5m/0.25 m/0.25 m, PMOS = 0.75m, PMOS = 0.75m/0.25 m/0.25 m, m, CCLL = 100 fF = 100 fF



Transistor Sizing BasicTransistor Sizing Basic Inverter as a reference circuit

Device Transconductance (See Supplement 1)

kknn = = kknn’’((WW//LL))nn = ( = (µµnnoxox//ttoxox)(()((WW//LL))nn

kkpp = = kkpp’’((WW//LL))pp = ( = (µµppoxox//ttoxox)(()((WW//LL))pp

For rise time equal to fall time,

kkpp = k = kn n (R(Rpp = R = Rnn))OutOutInIn

VVDDDD

(W/L)(W/L)pp

(W/L)(W/L)nn

CCLL

Because µµpp ~~ µµnn /2/2

((WW//LL))pp = 2= 2 ((WW//LL))nn

The size of PMOS must be twice as large as that of NMOSThe size of PMOS must be twice as large as that of NMOS

22

11



Transistor Sizing: NAND and NORTransistor Sizing: NAND and NOR

2

2

2 2

11

4

4CCLL

AA

RRnn

AA

RRpp

BB

RRpp

BB

RRnn CCintint

NANDNAND

RRpp

RRpp

RRnn RRnn CCLL

CCintint

BB

AA

AA BB

NORNOR

Symmetric Response Symmetric Response RRPUNPUN = = RRPDNPDN

RRpp 1/( 1/(WW//LL))pp

RRnn 1/( 1/(WW//LL))nn

RRPDNPDN = = RRnn + + RRnn

RRPUNPUN = = RRpp + + RRpp



Note on Transistor SizingNote on Transistor Sizing By assuming RPUN = RPDN, we ignores the extra

diffusion capacitance introduced by widening the transistors.

In DSM, even larger increases in the width are needed due to velocity saturationvelocity saturation. For 2-input NANDs, the NMOS transistors should

be made 2.5 times2.5 times as wide.

NAND implementation is clearly preferred NAND implementation is clearly preferred over a NOR implementationover a NOR implementation, since a PMOS stack series is slower than an NMOS stack due to lower carrier mobility



1

2

2 2

4

48

8

Transistor Sizing: Transistor Sizing: Complex CMOS GateComplex CMOS Gate

DD

AA

BB CC

DD

AA

BB

CC

6

612

12

Red sizingRed sizing assuming RPUN = RPDN

Follow short path first; note PMOS for C and B,4 rather than 3 (average in pull-up chain of three = (4+4+2)/3)

Also note structure of pull-up and pull-down to minimize diffusion cap. at output (e.g., single PMOS drain connected to output)

GreenGreen for symmetric response and for performance (where Rp = 3Rn) Sizing rules of thumb: PMOS = 3 *

NMOS



Fan-In ConsiderationsFan-In Considerations

DDCCBBAA

DD

CC

BB

AA CCLL

CC33

CC22

CC11

Distributed RC model Distributed RC model (Elmore delay)(Elmore delay)

ttpHLpHL = 0.69 = 0.69 RReqneqn((CC11+2+2CC22+3+3CC33+4+4CCLL))

Propagation delay deteriorates rapidly as a function of Propagation delay deteriorates rapidly as a function of fan-in – fan-in – quadratically quadratically in the worst case.in the worst case.



Notes on Fan-In ConsiderationsNotes on Fan-In Considerations While output capacitance makes full swing transition from

VDD to 0, internal nodes only swing from VVDDDD--VVTnTn to GND to GND

CC11, , CC22, and , and CC33, each includes junction capacitance as well as the gate-to-source and gate-to-drain capacitances (turned into capacitances to ground using the Miller effect) For W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, values are on

the order of 0.85 fF0.85 fF

CL = 3.47 fF3.47 fF with NONO output load (all of diffusion capacitance = intrinsic capacitance of the gate itself).

tpHL = 85 ps (simulated as 86 ps). The simulated worst case low-to-high delay was 106 ps.



ttpp as a Function of Fan-In as a Function of Fan-In

Gates with a fan-in Gates with a fan-in greater than 4greater than 4 should be avoided. should be avoided.

quadraticquadratic

linearlinear

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

ttpLHpLH

tt pp (

pse

c) (

pse

c)

fan-infan-in

ttpHLpHL ttpp



ttpp as a Function of Fan-Out as a Function of Fan-OutAll gates have the same drive current.All gates have the same drive current.

0

200

400

600

800

1000

1200

2 4 6 8 10 12 14 16

ttppNOR2NOR2

tt pp (

pse

c) (

pse

c)

eff. fan-outeff. fan-out

ttppNAND2NAND2

ttppINVINV

Slope is a function of “driving strength”Slope is a function of “driving strength”



ttpp as a Function of Fan-In and Fan-Outas a Function of Fan-In and Fan-Out

Fan-in:Fan-in: quadraticquadratic due to increasing resistance and capacitance

Fan-out:Fan-out: each additional fan-out gate adds twotwo gate capacitances to CL

ttpp = = aa11FI + FI + aa22FIFI22 + + aa33FOFO

Parallel ChainParallel Chain Serial ChainSerial Chain



Distributed RC lineDistributed RC line

M1 > M2 > M3 > … > MNM1 > M2 > M3 > … > MN

(the FET closest to the outputoutput should be the smallest)

Can reduce delay by more Can reduce delay by more than 20%; decreasing gains than 20%; decreasing gains as technology shrinksas technology shrinks

Fast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 1 Transistor sizing

as long as fan-out capacitance dominates

Progressive sizingProgressive sizing

InInNN CCLL

CC33

CC22

CC11InIn11

InIn22

InIn33

M1M1

M2M2

M3M3

MNMN



Notes on Design Technique 1Notes on Design Technique 1 With transistor sizing, if the load capacitance is dominated

by the intrinsic capacitanceintrinsic capacitance of the gate, widening the device only creates a “self loading”“self loading” effect and the propagation delay is unaffected (and may even become worse).

For progressive sizing, M1 have to carry the discharge current from M2 (CC11), M3 (CC22), … MN and CCLL so make it the largest. MN only has to discharge the current from MN (CCLL)(no internal

capacitances).

While progressive sizing is easy in a schematic, in a real layout it may not pay off due to design-rule considerations that force the designer to push the transistors apart increasing internal capacitance.



chargedcharged

chargedcharged

delay determined by time delay determined by time to discharge Cto discharge CLL, C, C11 and C and C22

delay determined by time delay determined by time to discharge Cto discharge CLL

dischargeddischarged

dischargeddischarged

Fast Complex Gates: Design Technique 2Fast Complex Gates: Design Technique 2 Input re-orderingInput re-ordering

when not all inputs arrive at the same time

CCLL

CC22

CC11InIn33

InIn22

InIn11

M1M1

M2M2

M3M3

critical pathcritical path

11

11

0011 chargedchargedCCLL

CC22

CC11InIn11

InIn22

InIn33

M1M1

M2M2

M3M3

critical pathcritical path

11

0011

chargedcharged11

Place latest arriving signal (critical path) Place latest arriving signal (critical path) closest to the output can result in a speed up.closest to the output can result in a speed up.



Example: Sizing and Ordering EffectsExample: Sizing and Ordering Effects

DDCCBBAA

DD

CC

BB

AA CCLL = = 100 100 fFfF

CC33

CC22

CC11

3 3 3 3

4

4

4

4

4

5

6

7

Progressive sizingProgressive sizing in pull-down in pull-down chain gives up to a 23% chain gives up to a 23% improvement.improvement.

Input orderingInput ordering saves 5% saves 5% critical path A – 23% critical path A – 23% critical path D – 17%critical path D – 17%



F = ABCDEFGHF = ABCDEFGH

Fast Complex Gates: Design Technique 3Fast Complex Gates: Design Technique 3 Alternative logic structuresAlternative logic structures

Reduced fan-in results in deeper logic depth

Reduction in fan-in offsets, by far, the Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate.extra delay incurred by the NOR gate.



Notes on Design Technique 3Notes on Design Technique 3 Reducing fan-in increases logic depth of the

circuit More stages but each stage has smaller delay

Only simulationsimulation will tell which of the two alternative configurations is faster and has lower power dissipation.



CCLLCCLL

Fast Complex Gates: Design Technique 4Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-outIsolating fan-in from fan-out using buffer

insertion Optimizing the propagation delay of a gate in isolation

is misguided.

Reduce Reduce CCLL on large fan-in gates, especially for large on large fan-in gates, especially for large CCLL, ,

and size the inverters progressively to handle the and size the inverters progressively to handle the CCLL

more effectivelymore effectively



tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL VVswingswing)/ IDSATn )

Fast Complex Gates: Design Technique 5Fast Complex Gates: Design Technique 5 Reducing the voltage swingReducing the voltage swing

linear reduction in delay also reduces power consumption

But the following gate is much slower!

Or requires the use of “sense amplifiers”“sense amplifiers” on the receiving end to restore the signal level (memory design)



Sizing Logic Paths for SpeedSizing Logic Paths for Speed Frequently, input capacitance of a logic path is

constrainedconstrained

Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is

0.5pF

How do we size the ALU data path to achieve maximum speed?

We have already solved this for the inverter chain – can we generalize it for any type of logic?



Inverter Chain: RecapInverter Chain: Recap

CCLL

InIn OutOut

1 2 N

11 f f f f NN-1-1

For given For given NN: : CCii+1+1//CCii = = CCii//CCii-1-1 = = f f = = ((CCLL//CCinin))NN

For optimum performance, we try to keep f ~ 4f ~ 4, which give us the number of stages, NN.

Can the same approach (logical effortlogical effort) be used for any combinational circuit?



Delay of a Complex Logic GateDelay of a Complex Logic Gate For a complex gate, we expand the inverter chain equation

€

t p = t p0 1+Cext

γ ⋅Cg

⎛

⎝ ⎜ ⎜

⎞

⎠ ⎟ ⎟= tp 0 1+

f

γ

⎛

⎝ ⎜

⎞

⎠ ⎟

ttpp00 is the intrinsic delay of an inverter

f f is the effective fan-out (Cext/Cg) - also called the electrical effortelectrical effort

pp is the ratio of the intrinsic (unloaded) delay of the complex gate and a simple inverter (a function of the gate topology and layout style)

gg is the logical effortlogical effort

€

t p = t p 0 p +g ⋅ f

γ

⎛

⎝ ⎜

⎞

⎠ ⎟



Notes on Delay of a Logic GateNotes on Delay of a Logic Gate

Gate delay:Gate delay: DD = = hh + + pp

Effort delay Intrinsic delay

Effort delay:Effort delay: hh = = g fg f

Logical Effort

ElectricalEffort

(effective fan-out)

Logical effort first defined by Sutherland and Sproull in 1999.

In a simpler format,

= Cout/Cin



Intrinsic Delay Term, pIntrinsic Delay Term, p The more involved the structure of the complex

gate, the higher the intrinsic delay compared to an inverter

Ignoring second order effects such as internal node capacitancesIgnoring second order effects such as internal node capacitances

Gate TypeGate Type pp

Inverter 1

n-input NAND n

n-input NOR n

n-way mux 2n

XOR, XNOR n 2n-1



Logical Effort Term, gLogical Effort Term, g Logical effort of a gate, gg, presents the ratio of its input

capacitance to the inverter capacitance when sized to deliver the same current gg represents the fact that, for a given load, complex gates have

to work harder than an inverter to produce a similar (speed) response

Gate TypeGate Typegg (for 1 to 4 input gates) (for 1 to 4 input gates)

11 22 33 44

Inverter 1

NAND 4/3 5/3 (n+2)/3

NOR 5/3 7/3 (2n+1)/3

Mux 2 2 2

XOR 4 12



Notes on Logical EffortNotes on Logical Effort InverterInverter has the smallest logical effort and intrinsic delay

of all static CMOS gates

Logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver same output current)

Logical effort is a function of topology, independent of sizing Logical effort increases with the gate complexityLogical effort increases with the gate complexity

Electrical effort (Effective fanout) is a function of load/gate size



A + BA + B

AA

BB

AA BB

AA

AA

AA

2

1

CCunitunit = 3 = 3

2 2

2

2

CCunitunit = 4 = 4

4

4

1 1

CCunitunit = 5 = 5

Example of Logical EffortExample of Logical Effort Assuming a PMOS/NMOS ratio of 2, the input capacitance of

a minimum-sized inverter is three times the gate capacitance of a minimum-sized NMOS (CCunitunit)

A • BA • B

AA

BB

AA BB



Delay as a Function of Fan-OutDelay as a Function of Fan-Out The slope of the line is

the logical effort of the gate

The y-axis intercept is the intrinsic delay

Can adjust the delay by adjusting the effective fan-out (by sizing) or by choosing a gate with a different logical effort

0

1

2

3

4

5

6

7

0 1 2 3 4 5

no

rma

lize

d d

ela

yn

orm

aliz

ed

de

lay

fan-out fan-out ff

NAND2: g=4/3, p

= 2

INV: g=1, p=1

intrinsic delayintrinsic delay

effort delayeffort delay

Gate Effort: Gate Effort: hh = = fgfg



1a b c

CCLL5

Path Delay: Complex Logic Gate NetworkPath Delay: Complex Logic Gate Network Total path delay through a combinational logic block

ttpp = = ttpp,j,j = = ttpp00 ((ppjj + ( + (ffjj g gjj)/)/ ) )

So, the minimum delay through the path determines that each stage should bear the same gate effort

ff11gg11 = = ff22gg22 = . . . = = . . . = ffNNggNN

Consider optimizing the delay through the logic network

how do we determine a, b, and c sizes?



Path Delay Equation DerivationPath Delay Equation Derivation The path logical effort, G = gi

And the path effective fan-out (path electrical effort) is F = CL/g1

The branching effort accounts for fan-out to other gates in the network

bb = ( = (CConon-path-path + + CCoffoff-path-path)/)/CConon-path-path

The path branching effort is then B = bi

The total path effort is then HH = = GFBGFB

So, the minimum delay through the path isNN

DD = = ttpp00 ( ( ppjj + (N + (N H)/ H)/ ))



Example: Complex Logic GatesExample: Complex Logic Gates For gate i in the chain, its size is determined by

For this network F = CF = CLL/C/Cg1g1 = 5 = 5

G = 1 x 5/3 x 5/3 x 1 = 25/9G = 1 x 5/3 x 5/3 x 1 = 25/9

B = 1B = 1 (no branching)

H = GFB = 125/9H = GFB = 125/9, so the optimal stage effort is H = 1.93H = 1.93 Fan-out factors are ff11=1.93, f=1.93, f22=1.93 x 3/5 = 1.16, f=1.93 x 3/5 = 1.16, f33 = 1.16, f = 1.16, f44 = 1.93 = 1.93

So the gate sizes are a = f1g1/g2 = 1.16, b = f1f2g1/g3 = 1.34 and c = f1f2f3g1/g4 = 2.60

44

j=1j=1

i -1i -1

ssii = (= (gg11 s s11)/)/ggii ( (ffjj/b/bjj))

1a b c

CCLL5



Example – 8-input ANDExample – 8-input AND



Summary: Method of Logical EffortSummary: Method of Logical Effort Compute the path effort: F = GBH

Find the best number of stages N ~ log4F

Compute the stage effort f = F1/N

Sketch the path with this number of stages

Work either from either end, find sizes:

Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.



Summary: Key DefinitionsSummary: Key Definitions

Sutherland,Sutherland,SproullSproullHarrisHarris



VDD

VSS

PDN

In1

In2

In3

F

RLLoad

ResistiveN transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

•

• tpL= 0.69 RLCL

Ratioed LogicRatioed Logic

NN transistors + Load

VVOHOH = = VVDDDD

VVOLOL = = RRPDN PDN / (/ (RRPDN PDN + + RRLL))

Asymmetrical Response

Static Power Static Power consumption consumption PPlowlow

tpL = 0.69 RLCL

Goal:Goal: To Reduce the number of devices over complementary CMOS To Reduce the number of devices over complementary CMOS



VDD

VSS

In1In2In3

F

VDD

VSS

PDN

In1In2In3

F

VSS

PDN

Depletion

LoadPMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0

Ratioed Logic: Active LoadsRatioed Logic: Active Loads

VDD

VSS

In1In2In3

F

VDD

VSS

PDN

In1In2In3

F

VSS

PDN

Depletion

LoadPMOSLoad

depletion load NMOS pseudo-NMOS

VT < 0



Pseudo NMOS NAND and NORPseudo NMOS NAND and NOR

DD

CC

BB

AA CCLL

FF

NANDNAND

DDCCBBAA CCLL

FF

NORNOR

Psedo-NMOS is useful when area is most important Reduce transistor counts Used occasionally for large fan-in gates



€

kn VDD −VTn( )VOL −VOL

2

2

⎛

⎝ ⎜

⎞

⎠ ⎟+ kp −VDD −VTp( ) ⋅VDSATp −

VDSATp2

2

⎛

⎝ ⎜

⎞

⎠ ⎟= 0

€

VOL =kp VDD + VTp( ) ⋅VDSATp

kn VDD −VTn( )≈

μnW p

μ pWn

⋅VDSATp

€

Plow = VDDIlow ≈ VDD ⋅ kp −VDD −VTp( ) ⋅VDSATp −VDSATp

2

2

⎛

⎝ ⎜

⎞

⎠ ⎟

Pseudo-NMOS Inverter CharacteristicsPseudo-NMOS Inverter Characteristics Assumptions:

NMOS resides in linear mode VOL is small relative to the gate drive (VDD-VT))



Pseudo-NMOS Inverter VTCPseudo-NMOS Inverter VTC

0.0 0.5 1.0 1.5 2.0 2.50.0

0.5

1.0

1.5

2.0

2.5

3.0

W/Lp = 4

W/Lp

= 2

W/Lp = 1

W/Lp = 0.25

W/Lp = 0.5

VVou

tou

t (V

) (

V)

VVinin (V) (V)

SizeSizeVVOLOL

(V)(V)

PPstatstat

((µµW)W)

ttpLHpLH

(ps)(ps)

44 0.693 564 14

22 0.273 298 56

11 0.133 160 123

0.50.5 0.064 80 268

0.250.25 0.031 41 569

NMOS size = 0.5 NMOS size = 0.5 µµm/0.25 m/0.25 µµmm

Larger pull-up device not only improves performance (delay) Larger pull-up device not only improves performance (delay) but also increases but also increases power dissipationpower dissipation and lowers and lowers noise marginsnoise margins by increasing Vby increasing VOLOL



M1 >> M2M1 >> M2

The idea is to reduce static power consump-tion by adjusting the load Load M2 when there are

not too many inputs (A, B, C, or D) active

Switch to Load M1 when all inputs are active (thus require high amount of current to drive)

Improved Loads: Adaptive LoadImproved Loads: Adaptive Load

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load

Enable



Improved Loads: DCVSLImproved Loads: DCVSLVDD

VSS

PDN1

Out

VDD

VSS

PDN2

Out

AABB

M1 M2

Differential Cascode Voltage Switch Logic (DCVSL)



B

A A

B B B

Out

Out

XOR-NXOR gate

DCVSL ExampleDCVSL Example



DCVSL CharacteristicsDCVSL Characteristics Dual Rail Logic

Each input is provided in complementary format and each gate produces complementary output

Increasing complexityIncreasing complexity

Rail-to-Rail SwingRail-to-Rail Swing

No static power dissipationNo static power dissipation

Sizing of the PMOS relative to PDN is critical to functionality, not just performance PDNs must be strong enough to bring outputs below

VDD - |VTp|



DCVSL Transient ResponseDCVSL Transient Response

0 0.2 0.4 0.6 0.8 1.0-0.5

0.5

1.5

2.5

Time [ns]

Vol

tag e

[V] A B

A B

A,BA,B

Transient Response of a 2-input AND/NAND gate. How does it look like? Transient Response of a 2-input AND/NAND gate. How does it look like?

ttinin->out->out = 197 ps = 197 ps

ttinin->out->out = 321 ps = 321 ps



A B

X YX = Y if A and BX = Y if A and B

X Y

A

B X = Y if A or BX = Y if A or B

NMOS Transistors in Series/ParallelNMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals

NMOS switch closes when the gate input is high

Remember - NMOS transistors pass a Remember - NMOS transistors pass a strong 0strong 0 but a but a weak 1weak 1



PMOS Transistors in Series/ParallelPMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals

PMOS switch closes when the gate input is low

Remember - PMOS transistors pass a Remember - PMOS transistors pass a strong 1strong 1 but a but a weak 0weak 0

X = Y if A and B = A + BX = Y if A and B = A + B

X = Y if A or B = A X = Y if A or B = A B B

A B

X Y

X Y

A

B



AA

00

BB

BB F= AF= ABB0.5/0.25

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

0 1 2

B = B = VVDDDD, A = 0, A = 0VVDDDD

A = A = VVDDDD, B = 0, B = 0VVDDDD

A = B = 0A = B = 0VVDDDDVV

ou

to

ut,

(V)

, (V

)

VVinin, (V), (V)

Pure PT logic is not Pure PT logic is not regenerativeregenerative - the signal - the signal gradually degrades after passing through a number gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)of PTs (can fix with static CMOS inverter insertion)

VTC of PT AND GateVTC of PT AND Gate



Complementary PT Logic (CPL)Complementary PT Logic (CPL)

BB

AAAABB PT NetworkPT Network FF

FF

BB

AAAABB

InverseInversePT NetworkPT Network FF

FF

AA

AA

BB F=A+BF=A+B

BB

BBBB

OR/NOROR/NOR

F=A+BF=A+B

AA

AA

BB F=A·BF=A·B

BB

BBBB

AND/NANDAND/NAND

F=A·BF=A·B

F=AF=ABB

F=AF=ABB

AA

AA

AA

AA

BBBB

XOR/XNORXOR/XNOR



CPL PropertiesCPL Properties Differential,Differential, so complementary data inputs and outputs are

always available (don’t need extra inverters)

StaticStatic, since the output defining nodes are always tied to VDD or GND through a low resistance path

Design is modularmodular; all gates use the same topology, only the inputs are permuted.

Simple XOR makes it attractive for structures like adders adders

Fast! Fast! (assuming number of transistors in series is small)

Additional routing overheadrouting overhead for complementary signals

Still have static power dissipation problems



NMOS-Only PT Driving an InverterNMOS-Only PT Driving an Inverter

Threshold voltage drop causes static power consumption (MM22 may be weakly conducting forming a path from VDD to GND)

Notice VTn increases of pass transistor due to body effectbody effect (VSB)

VVxx does not pull up to V does not pull up to VDDDD, but , but VVDDDD – V – VTnTn

VVGSGS

InIn = = VVDDDD

A = A = VVDDDDVVxx

MM11

MM22

B

SD OutOut



Voltage Swing of PT Driving an InverterVoltage Swing of PT Driving an Inverter

Body effectBody effect – large VSB at XX - when pulling high (B is tied to GND and S charged up close to VDD)

So the voltage drop is even worse

VVxx = = VVDDDD - ( - (VVTn0Tn0 + + (((|2(|2ff| | + + VVxx) - ) - |2|2ff|))|))

0

1

2

3

0 0.5 1 1.5 2Time (ns)Time (ns)

Vo

ltag

e (V

)V

olt

age

(V)

InIn

OutOut

XX = 1.8V = 1.8VIn = 0 In = 0 V VDDDD

VVDDDD

XXOutOut

0.5/0.250.5/0.25

1.5/0.25

D

S

B



Cascaded NMOS-Only PTsCascaded NMOS-Only PTsB = B = VVDDDD

OutOut

M1

yyM2

A = A = VVDDDD

C = C = VVDDDD

xx

GG

SSGG

SS

xxM1

B = B = VVDDDD

OutOutyyM2

C = C = VVDDDD

A = A = VVDDDD= = VVDDDD - - VVTnTn11

Swing on y = Swing on y = VVDD DD - V- VTn1Tn1 - V - VTn2Tn2 Swing on y = Swing on y = VVDD DD - V- VTn1Tn1

Pass transistor gates should nevernever be cascaded as on the left

Logic on the right suffers from static power static power dissipationdissipation and reduced noise marginsreduced noise margins



M1

M2

AA Mn

xx

BB

OutOut

Solution 1: Level RestorerSolution 1: Level Restorer

For correct operation Mr must be sized correctly (ratioedratioed)

Full swing on xx (due to Level Restorer) so no static no static power consumptionpower consumption by inverter

No static backward currentNo static backward current pathpath through Level Restorer and PT since Restorer is only active when AA is high

Level Level RestorerRestorer

Mr

AA BB XX OutOut MMrr

0 0VDD 0 VDD OFFOFF

VDD 0VDD VVDDDD 0 ONON



Transient Level Restorer Circuit ResponseTransient Level Restorer Circuit Response

0

1

2

3

0 100 200 300 400 500

Vo

ltag

e (V

)V

olt

age

(V)

Time (ps)Time (ps)

W/LW/Lrr=1.75/0.25=1.75/0.25

W/LW/Lrr=1.50/0.25=1.50/0.25

W/LW/Lrr=1.25/0.25=1.25/0.25W/LW/Lrr=1.0/0.25=1.0/0.25

node node xx never goes below never goes below VVMM of inverter so output of inverter so output

never switchesnever switches

Restorer has speed and power impacts: Increases the capacitance at xx, slowing down the gateslowing down the gate

Increases ttrr (but decreases ttff)

W/LW/Lnn=0.50/0.25, =0.50/0.25, W/LW/L11=0.50/0.25,=0.50/0.25, W/LW/L22=1.50/0.25=1.50/0.25



Notes on Level RestorerNotes on Level Restorer Pull down must be strongerstronger than restorer (pull up)

to switch node XX

If resistance of restorer transistor is too small (too wide transistor) it is impossible to bring the voltage at node XX below the switching threshold of the inverter, and the inverter never switches!the inverter never switches!

Sizing of MMrr is critical for DC functionality, not just performance!!

It belongs to Dynamic LogicDynamic Logic Family



Solution 2: Multiple VSolution 2: Multiple VTT Transistors Transistors Technology solution: Use (near) zero VT devices for the NMOS

PTs to eliminate mostmost of the threshold drop (body effect still in force preventing full swing to VDD)

OutOut

InIn22 = 0V= 0V

InIn11 = 2.5V= 2.5V

AA = 2.5V= 2.5V

BB = 0V= 0V

low Vlow VTT

transistorstransistors

sneak sneak pathpath

onon

off butoff butleakingleaking

Watch out for subthreshold Watch out for subthreshold current flowing through PTscurrent flowing through PTs



Solution 3: Transmission Gates (TGs)Solution 3: Transmission Gates (TGs)

Full swingFull swing bidirectionalbidirectional switch controlled by the gate signal C, A = B if C = 1

AA BB

CC

CC

BB

C = C = VVDDDD

C = C = GNDGND

A = A = VVDDDD BB

C = C = VVDDDD

C = C = GNDGND

A = GNDA = GND

Most widely used solution

AA BB

CC

CC



Resistance of TGResistance of TG

0

5

10

15

20

25

30

0 1 2

VVoutout (V) (V)

Res

ista

nce

(k

Res

ista

nce

(k

))

RRpp

RRnn

RReqeq

RRpp

RRnn

2.5V2.5V

0V0V

2.5V2.5V VVoutout

W/Ln=0.50/0.25

W/Lp=0.50/0.25

TG is not an ideal switch - series resistanceseries resistance

RReqeq is relatively constant ( about 8kohms in this case), so can assume has a constant resistanceconstant resistance

RReqeq = = RRpp || || RRnn



SS

SS

SS

InIn22

InIn11

FF

F = !(InF = !(In1 1 S + In S + In22 S) S) GND

VDD

In1 In2S S

S S F

TG MultiplexerTG Multiplexer



off

off

BB

AA A A B B

Transmission Gate XORTransmission Gate XOR

FF always has a connection to VDD or GND - not dynamicnot dynamic

No voltage dropNo voltage drop

6 Transistors6 Transistors




BB

AA F = A‘ F = A‘

VVDDDD (B)(B)

0 0 (B’)(B’)

When BB = 1= 1, the circuit behaves as if it is an inverteran inverter, hence FF(B B = 1= 1) = A’A’

off

off

1




When BB = 0= 0, the circuit acts as a transmission gate, hence FF(B B = 0= 0) = A A (TG ensures no voltage drop)

BB

AA F = AF = A

when A = 0weak 0

weak 1 when A = 1

VVDDDD (B’)(B’)

0 0 (B)(B)

on

on

0




BB

AA A‘ B + A B’A‘ B + A B’

Combine the results using Shannon’s expansion theorem,

FF = = BB··FF((B B = 1)= 1) + + B’B’··FF((BB = 0) = 0) = = A’BA’B++AB’AB’ = = A A BB



TG Full AdderTG Full Adder

SumSum

CCoutout

AA

BB

CCinin

• 16 Transistors, no more than 2 PTs in series16 Transistors, no more than 2 PTs in series• Full swingFull swing• Similar delay for Sum and CarrySimilar delay for Sum and Carry



Delay of a TG ChainDelay of a TG Chain

CC CC CC CC

VVNN

VV11 VVii VVi+1i+1

55

00

55

00

55

00

55

00

VVinin

Delay of the RC chain (NN TG’s in series) is

ttpp((VVnn) = 0.69 ) = 0.69 kCRkCReqeq = 0.69 = 0.69 CRCReqeq ( (NN((NN+1))/2 +1))/2 0.35 0.35 CRCReqeqNN22

RReqeq RReqeq RReqeq RReqeqVVinin

CC CC CC CC

VV11 VVii VVi+1i+1

VVNN



Notes on TG Chain DelayNotes on TG Chain Delay Delay grows quadratically in Nquadratically in N (in this case in the

number of TGs in series) and increases rapidly with the number of switches in the chain.

E.g., for 16 cascaded minimum-sized TG’s, each with an Req of 8kohms.

The node capacitance is the sum of the capacitances of two NMOS and PMOS devices (junctions and drains).

Capacitance values is approx. 3.6 fF for low to high transitions.

The delay through the chain is tp = 0.69 CReq(N(N+1))/2 = 0.69 x 3.6fF x 8kΩ x (16x17)/2 =

2.7ns



Delay of buffered chain (MM TG’s between buffer)

ttpp = 0.69 = 0.69 N/M CRN/M CReqeq ( (MM((MM+1))/2+1))/2 + ( + (N/MN/M - 1) - 1) ttpbufpbuf

MMoptopt = 1.7 = 1.7 ( (ttpbufpbuf//CRCReqeq )) 3 or 4 3 or 4

TG Delay OptimizationTG Delay Optimization Can speed it up by inserting buffers every M switches

VVinin

VVNN

M

CC55

00

55

00

55

00

CC CC55

00

55

00

55

00

CC CCCC



Notes on Delay Optimization Notes on Delay Optimization Buffered chain is now linear in Nlinear in N

Quadratic in MM but M should be smallM should be small

This buffer insertion technique works to speed up the delay down long wires as well.

Consider 16TG chain example. Buffers = inverters (making sure correct polarity is output). For 0.5micron/0.25micron NMOSs and PMOSs in the TGs,

simulated delay with 2TG per buffer is 154 ps154 ps,

for 3TGs is 154ps154ps, and for 4TG is 164ps164ps.

The insertion of buffering inverters reduces the delay by a The insertion of buffering inverters reduces the delay by a factor of almost 2.factor of almost 2.

Chapter 6 Static CMOS Circuits Boonchuay Supmonchai Integrated Design Application Research (IDAR)...

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Transcript of Chapter 6 Static CMOS Circuits Boonchuay Supmonchai Integrated Design Application Research (IDAR)...