Tutorial 3 VLSI Design Methodology Boonchuay Supmonchai June 10th, 2006.
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Transcript of Tutorial 3 VLSI Design Methodology Boonchuay Supmonchai June 10th, 2006.
Tutorial 3Tutorial 3
VLSI Design MethodologyVLSI Design Methodology
Boonchuay SupmonchaiJune 10th, 2006
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B.SupmonchaiB.Supmonchai
OutlinesOutlines VLSI Design Flow and Structural Design VLSI Design Flow and Structural Design
PrinciplesPrinciples
VLSI Design Styles
VLSI Design Strategies
Computer-Aided Design Technology for VLSI
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Simplified VLSI Design FlowsSimplified VLSI Design Flows
System Specification
Functional (Architecture) Design
Functional Verification
Logic Design
Logic Verification
Circuit Design
Circuit Verification
Physical Design
Physical Verification
Front EndFront End Back EndBack EndSynthesis PhaseSynthesis Phase Layout PhaseLayout Phase
BehavioralBehavioralRepresentationRepresentation
LogicLogic(Gate-Level)(Gate-Level)
RepresentationRepresentation
CircuitCircuitRepresentationRepresentation
LayoutLayoutRepresentationRepresentation
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Four Levels of Design RepresentationFour Levels of Design Representation
BehavioralBehavioralRepresentationRepresentation
Logic (Gate-Level)Logic (Gate-Level)RepresentationRepresentation
Circuit Circuit (Transistor-Level) (Transistor-Level) RepresentationRepresentation
Layout Layout RepresentationRepresentation
Functional Blocks, FSMFunctional Blocks, FSM
Logic Blocks, GatesLogic Blocks, Gates
Transistor SchematicsTransistor Schematics
Physical DevicesPhysical Devices
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Structure Design PrinciplesStructure Design Principles HierarchyHierarchy:
““Divide and conquer”Divide and conquer” technique involves dividing a module into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable.
RegularityRegularity: The hierarchical decomposition of a large system should result
in not only simplesimple, but also similarsimilar blocks, as much as possible.
Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction.
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Example of RegularityExample of Regularity
These circuits are built using inverters and tri-state buffers only.These circuits are built using inverters and tri-state buffers only.
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Structured Design Principles (Cont.)Structured Design Principles (Cont.) ModularityModularity:
The various functional blocks which make up the larger system must have well-defined functionswell-defined functions and interfacesinterfaces..
Modularity allows each block to be designed independently; All blocks can be combined with ease at the end of the process.
LocalityLocality: Internal details remain at the local level.
The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance avoiding long-distance connectionsconnections as much as possible.
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Example: 16-bit Adder CircuitExample: 16-bit Adder Circuit
Structural Hierarchy of a 16-bit Manchester AdderStructural Hierarchy of a 16-bit Manchester Adder
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Example (Cont.): Level 1Example (Cont.): Level 1
16-bit Adder16-bit AdderComplete LayoutComplete Layout
4-bit Adder with Manchester carry4-bit Adder with Manchester carry
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Example (Cont.): Level 2Example (Cont.): Level 2
4-bit Adder with Manchester Carry Layout4-bit Adder with Manchester Carry Layout
Carry/propagate circuitCarry/propagate circuit Output buffer/latchOutput buffer/latch
Manchester Carry circuitManchester Carry circuit
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Example (Cont.): Level 3Example (Cont.): Level 3
Carry/propagate Carry/propagate circuit layoutcircuit layout
Manchester carry Manchester carry circuit layoutcircuit layout
Output buffer/latch Output buffer/latch circuit layoutcircuit layout
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OutlinesOutlines VLSI Design Flow and Structural Design
Principles
VLSI Design StylesVLSI Design Styles
VLSI Design Strategies
Computer-Aided Design Technology for VLSI
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VLSI Design StylesVLSI Design Styles
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Full-Custom DesignFull-Custom Design Full-custom blocks are carefully crafted in the
physical level to obtain the highest possible performance.
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Full-Custom Design Key IssuesFull-Custom Design Key Issues The key to Full-custom design is to exploit the
fine-grained regularity and modularity in the physical level.
Manual full-custom design can be very challenging and time consuming, especially if the low level regularity is not well defined. Development cost are too high!
Design reuse is becoming popular to reduce design cycle time and development cost. IP blocksIP blocks
Full-custom design is used only in the critical blocks.
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Full-Custom DRAM ExampleFull-Custom DRAM Example
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Cell-Based DesignCell-Based Design “Lego” Style Design
All of the commonly used logic cells are developed, characterized, and stored in a standard cell library. Library contains a certain numbers of basic cells
such as inverters, NAND, NOR, each in several versions to provide a range of performance. The inverter gate can have standard size, double size, and
quadruple size.
Most popular because of CAD tools availability and capability.
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Cell-Based Design Key IssuesCell-Based Design Key Issues Inclusion/Exclusion of a gate variation depends
on the objectives of the library. Standard Library, Low Power Library, etc.
Most challenging task is to how to place the individual cells into rows and interconnect them in a way that meet stringent design goals. Most advanced CAD tools have place-and-route tools.
In a complex, demanding design, standard-cell based design approach may be used as a first pass, then full-custom design where necessary.
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Example of Standard CellsExample of Standard Cells
Each cell layout is designed with a fixed height so that a Each cell layout is designed with a fixed height so that a number of cells can be “snapped” together side-by-side number of cells can be “snapped” together side-by-side to form rows.to form rows.
Power RailPower Rail
Ground RailGround Rail
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Example of Stand Cells (Cont.)Example of Stand Cells (Cont.)
Standard CellStandard Cell
Routing ChannelRouting Channel
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Cell-Based Design ExampleCell-Based Design Example
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Masked Gate Array (MGA) DesignMasked Gate Array (MGA) Design
Only transistorsOnly transistorsNo contacts and metal layersNo contacts and metal layers
One pattern mask forOne pattern mask forMass productionMass production
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MGA Design Key IssuesMGA Design Key Issues “Uncommitted” (Unused) transistors or gates are
wasted. Performance measured as Chip Utilization Factor ~
used chip area/total chip area.
Uncommitted cells can be sacrifices to improve intercell routing capability
Modern GAs use multiple metal layers for channel routing Smaller area, higher density, and routability
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Example of MGA DesignExample of MGA Design
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FPGA DesignFPGA Design An FPGA chip provides thousands of logic
gates, organized into logic blocks, with programmable interconnects.
To implement a custom hardware, a user can use high-level hardware programming (e.g., HDL). Program logic table for each logic block.
Program interconnect switch matrices
Program I/O blocks
Programs last as long as the chip is powered-on
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Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)
Architecture of Xilinx FPGAsArchitecture of Xilinx FPGAs
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FPGA (Cont.)FPGA (Cont.)
Simplified block diagram of a CLB by XilinxSimplified block diagram of a CLB by Xilinx
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FPGA (Cont.)FPGA (Cont.)
Switch matrices and interconnection routing between CLBSwitch matrices and interconnection routing between CLB
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FPGA Design Key IssuesFPGA Design Key Issues Chip utilization of an FPGA depends on
GranularityGranularity of the logic block - Size of logic block Routing capabilityRouting capability - Size of switch matrices
The largest advantage of FPGA-based design is the very short turn-around timeturn-around time
The time required from the start of the design process until a functional chip is available
Typical price of FPGA chips is usually higher than other alternatives of the same design, but for small-volume production and for fast prototyping
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HDL-Based DesignHDL-Based Design1980’s1980’sHardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups.
1990’s1990’sThe increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design.
2000’s2000’sModern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements.
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HDL-Based Design MethodologyHDL-Based Design Methodology
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OutlinesOutlines VLSI Design Flow and Structural Design
Principles
VLSI Design Styles
VLSI Design StrategiesVLSI Design Strategies
Computer-Aided Design Technology for VLSI
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VLSI Design StrategiesVLSI Design Strategies Phenomenal growth rate in VLSI leads to a very
complex and lengthy development of ICs. Design complexity increases almost exponentiallyexponentially
with the number of transistors to be integrated.
Efficient organization of all efforts is essential to the survival of a company. Teamwork
Better tools
Innovatives and creativities.
Better StrategiesBetter Strategies
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Product Life-CycleProduct Life-Cycle
Products have a shorter life-cycleProducts have a shorter life-cycle
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Comparison of Design StrategiesComparison of Design Strategies
Freedom of Choices….Freedom of Choices….
Custom DesignCustom Design
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Comparison (Cont.)Comparison (Cont.)
Cell DesignCell Design
FPGA DesignFPGA Design
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System-On-Chip (SOC) DesignSystem-On-Chip (SOC) Design Integrating all or most of the components of a
hybrid system on a single substrate (silicon or MCM), rather than building a conventional printed circuit board.
Consequences: More compact system realization
Less expensive!
Higher speed / performance Better reliability
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Example of SOC DesignExample of SOC Design
Digital Video ProcessorDigital Video Processor
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Example of SOC Design (Cont.)Example of SOC Design (Cont.)
Each functional block can be reused block, IP Each functional block can be reused block, IP (Intelectual Property) block, or custom-designed (Intelectual Property) block, or custom-designed block. block.
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OutlinesOutlines VLSI Design Flow and Structural Design
Principles
VLSI Design Styles
VLSI Design Strategies
Computer-Aided Design Technology for VLSIComputer-Aided Design Technology for VLSI
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Computer-Aided Design TechnologyComputer-Aided Design Technology CAD tools become more and more
indispensable for timely development of ICs.
Remember! CAD tools are good helpers for CAD tools are good helpers for time-consuming and computation intensive time-consuming and computation intensive mechanistic parts of the design, mechanistic parts of the design, not the creative not the creative and inventive parts!and inventive parts!
CAD technology divides into three categories: Synthesis Tools (Synopsys®)Synthesis Tools (Synopsys®)
Layout Tools (Cadence®)Layout Tools (Cadence®)
Simulation and Verification ToolsSimulation and Verification Tools
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Synthesis ToolsSynthesis Tools High-Level SynthesisHigh-Level Synthesis tools automate the design
phase in the top level of the design hierarchy: Based on Hardware-Description Languages (HDL)
VHDLVHDL, VerilogVerilog, etc.
Determining the types and quantities of modules to be included in the design using accurate estimate of lower level design features (area and delay).
Logic Synthesis and optimizationLogic Synthesis and optimization tools can then be used to customize the design to particular needs, such as area minimization, low power, etc.
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Layout ToolsLayout Tools Circuit OptimizationCircuit Optimization tools deal with the design
in the transistor schematic levels: Transistor sizing for delay minimization
Reliability issues: process variations, noise.
LayoutLayout tools concern with the physical level of the design, i.e., how circuits are actually built on the IC: Standard Layout CAD tools are Floorplanning,
Place-and-route, and Module generation
Sophisticated Layout CAD tools are goal driven and include some degree of optimization functions
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Simulation and Verification ToolsSimulation and Verification Tools Time spent on debugging and correcting a
design has been increasing exponentiallyexponentially as each generation passed. Higher penalty is paid if a design flaw is detected
later in the design process.
Simulation and verification are the most mature area in VLSI CAD
Goal of all simulation tools is to determine if the design meets the required specifications at a particular design stage.
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Simulation Tools (Cont.)Simulation Tools (Cont.) Simulation tools used at various stages of the
design process are Behavior simulationBehavior simulation tools
Logic Level simulationLogic Level simulation tools Complement logic synthesis and optimization tools.
Circuit-level simulationCircuit-level simulation tools SPICE or derivatives such as HSPICE, PSPICE, etc.
Design Rule CheckingDesign Rule Checking tools Layout rule checking, Electrical Rule CheckingElectrical Rule Checking (ERC),
reliability rule checking.