Benchmarking Spintronic Logic Devices

Benchmarking Spintronic Logic Devices

Dmitri Nikonov and Ian Young

Exploratory Integrated Circuits Group

Components Research

Technology & Manufacturing Group

Intel Corporation

Hillsboro, Oregon

Nikonov, NCN Summer School, 2014 1

Outline

1. Spin and other computational variables, non-volatile logic.

2. Spintronic device switching mechanisms.

3. Types of spintronic devices.

4. Spintronic circuits, layout, area.

5. Estimates for switching speed and energy, dissipated power, and computational throughput.


Why Are We Looking Beyond CMOS

0

50

100

150

200

250

300

0.0 0.3 0.6 0.9

CM

OS

Cir

cuit

De

lay

(p

s)

Supply Voltage (V)

Aiming to maintain computational throughput at lowest supply voltage (Vdd)

• Switching energy ~CVdd2 determines active power

• At Vdd ≤ Vth (threshold voltage), switching speed suffers significantly

• Lowest Vth is limited by leakage = standby power (60 mV/dec Id/Vgs sub-

threshold slope)

For ITRS LG=20nm at 1nW Standby Power

Vth


Nanoelectronic Research Initiative

UC Los Angeles UC Berkeley

UC Irvine UC Riverside

UC Santa Barbara Portland State

U. Nebraska-Lincoln U. Wisconsin-Madison

Notre Dame Purdue Penn State UT-Dallas

UT-Austin Rice UT-Dallas Texas A&M

U. Maryland NCSU

SUNY-Albany Purdue MIT Columbia Harvard GIT U. Virginia

NCSU

(co-funds all centers)

Virginia Nanoelectronics Center (ViNC)

University of Virginia Old Dominion University College of William & Mary

Brown Columbia Illinois-UC

MIT/U.Virginia Nebraska-Lincoln

Northwestern Penn State

Princeton / UT-Austin Purdue

Stanford U. Alabama UC Berkeley

2007-present, few $M, 5 semiconductor co., federal and state governments


1. Spin and other computational variables,

non-volatile logic

Electric switching is single-electron, magnetic switching is a collective mode. Energy barrier and consequences for bit errors. Magnetic as well as

ferroelectric are non-volatile. Why non-volatility is important for computing systems.


Computational Variables

Charge Electric Dipole

Magnetic Dipole

Orbital State

Class Variables Example

Charge Q, I, V CMOS, TFET

Electric Dipole P FeFET

Magnetic Dipole M, Ispin ASL, SWD, NML

Orbital State Orb, Bose condensate BisFET

Strain s PiezoFET

e-

Strain


Barriers, Collectives, Thermodynamics source gate drain

e-

Energy

θ 0/ 2

)exp(kT

VeII offon

kTHNE ksB 60~2

10

kTVNeEe

16000~

Generic Electronic Switch Generic Spintronic Switch

Barrier 40 kT (from Ion/Ioff) 60 kT (non-volatile)

Voltage 0.5 – 1 V 10-100 mV

Particles Ne = 400 electrons Ns = 10,000 spins

Sw. Energy Limit 16,000kT = Ne*40kT 60 kT

Phenomenon Non collective Collective

e-

Leakage not related to barrier

Leakage determined by barrier

(1)

(2)

(3)

Magnetization angle


5 Beyond-CMOS Devices, Electronic & Orbitronic

Orbitronic BisFET

Graphene pn Junction Homojunction Tunneling FET

Heterojunction Tunneling FET

Graphene Nanoribbon Tunneling FET

Electronic


8 Beyond-CMOS Devices, Spintronic

All Spin Logic

e

e

Spin Wave Device

SpinFET

Nano Magnet Logic

Spintronic Majority Domain Wall Logic

Spin Torque Triad

Spin Torque Oscillator


6 New Devices Added in 2013 Electronic

ITFET

FEFET Negative Cap FET

3. Orbitronic

MITFET

Ferroelectric

Charge-spin logic

Spintronic Straintronic

PiezoFET


Nomenclature of Beyond-CMOS Devices


Computational Variables and Transduction

A. Transistor-like devices: (CMOS HP, CMOS LP, III-V FET, HJFET, gnrFET, spinFET) also GpnJ, BisFET

Output of a device needs to be the same computational variable (and same range) as input. Otherwise a transducer is needed.

B. STT/DW, STOlogic, CSL Current-driven = Spin Torque Switching

C. SMG, SWD, NML Voltage-driven = Magneto-Electric Switching; also ASL (current driven)


Non-Volatile Circuits

A.


TkNP

B

expexp)(0

30 35 40 45 50 55 6010

-5

100

105

1010

/kT

Arr

ay R

ete

ntio

n tim

e, s

10years

Probability for a circuit, N elements, to retain

TkN

P

B

ret exp)log(

0

Retention probability 99%, N=1024x1024 circuit

Retention time for a circuit ns1~0

Energy

θ 0/ 2

Magnetization angle

Sleep States with Non-Volatile

• Standby power is a big problem, especially for mobile systems

• Microprocessor is working in bursts, idle most of the time

• Presently MPU is put into sleep states by gating power supply

• Data need to be stored in main memory

• Non-volatile circuits enable storing data on chip

• Not spending time and energy to store

• Can put MPU to sleep more often !!!

H. Yoda et al., IEDM 11.3 (2013).


2. Spintronic device switching mechanisms

Summary and comparison of spin torque, spin Hall, magnetostrictive, multiferroic, voltage-

controlled surface anisotropy. Corresponding time and energy of switching.


I Q

Gnd

Cic Cg

Vdd

Vs

-Q I

Gnd

Cic Cg

Vdd

Vs

+ +

+

- -

-

Q Cfe

Electronic vs. Ferroelectric Circuits

• Current through first transistor to charge gate of the next

• Transmits electrical signal

• Similar to electronic • Non-volatile ferroelectric state • Speed limited : intrinsic

ferroelectric time

Electronic

Ferroelectric


pst fe 50

Electronic

Ferroelectric

I Q

Gnd

Cic Cg

Vdd

Vs

-Q I

Gnd

Cic Cg

Vdd

Vs

+ +

+

- -

-

Q Cfe

Electronic vs. Ferroelectric Circuits

ICVt ddel

2

ddel CVE

Switching time

Switching energy

IQtch

ddel QVE

Charging, intrinsic time

Switching energy

dds CVAPQ

Charge


Gnd

I

Vdd

Vcl

+ + + + - - - -

Gnd

Q Cc

-Q

I

Vdd

Vcl

Spintronic Writing Circuits

• Current switches magnetization • Current is clocked power source • Magnetic signal transmitted • Non-volatile magnetization • Energy limit by Joule heating

• Current charges FE capacitor • Similar to current driven:

electrical circuits are support, not logic

• Time limited by M rotation

Current driven - spin torque

Voltage driven – magnetoelectric


Current driven - spin torque

Voltage driven – magnetoelectric

Gnd

I

Vdd

Vcl

+ + + + - - - -

Gnd

Q Cc

-Q

I

Vdd

Vcl

Spintronic Writing Circuits

b u nmU K v

bc

e UI

P

energy barrier

critical current

2 2log

3

Bs nmstt

B c c b

k TeM vt

g P I I U

stt dev dd sttE I V t

0ms ms msP = E polarization

charge

2mag

me

tB

dds CVAPQ

ddme QVE


Switching with Exchange Bias

E-field changes spins at interface, local B-field

FE- AFM

FM

BME

M

V

1. Multiferroic (like BiFeO3) has ferroelectric (FE) and antiferromagnetic (AFM) orders

2. Spins at interface interact with spins in the ferromagnet (FM). Results in an effective magnetic field (BME) aka “exchange bias” experimentally<0.03T up to now

3. Electric field switches FE and AFM

4. Effective field switches magnetization (M)

E

+ + + +

- - - -


10 -2

10 -1

10 0

10 1

10 -1

10 0

10 1

10 2

Voltage, V

Cu

rre

nt,

A

CMOS HP

CMOS LP

HomJTFET

HetJTFET

gnrTFET

ITFET

GpnJ FEFET NCFET

PiezoFET

BisFET

MITFET

SpinFET

ASL

CSL

STT/DW

SMG

STOlogic

SWD NML

Current vs. Voltage, Devices

High resistance

Low resistance

Spin Torque 10mV

Magnetoelectric 100mV

Electronic 100-1200mV

Spintronics enables lower voltage

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 -2

10 -1

10 0

10 1

10 1

10 2

10 3

10 4

10 5

Voltage, V

Ch

arg

e, e

CMOS HP

CMOS LP

HomJTFET

HetJTFET gnrTFET ITFET

GpnJ

FEFET

NCFET

PiezoFET BisFET

MITFET

SpinFET

ASL CSL

STT/DW

SMG

STOlogic

SWD

NML

Charge vs. Voltage

High energy

Shot noise?

Low capacitance

High capacitance

Spin torque = high capacitance

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


Charge-Resistance Approach

Ohm’s law

Q I

V IR

Switching charge

E IV Dissipated energy

Unless time of current pulse is not equal to switching time

/QR V

E QV

2E Q R

For small resistance and low voltage devices resistance of power and ground wires cannot be neglected


10 2

10 3

10 4

10 5

10 6

10 1

10 2

10 3

10 4

10 5

Resistance, Ohm

Ch

arg

e, e

CMOS HP

CMOS LP

HomJTFET

HetJTFET

gnrTFET

ITFET

GpnJ

FEFET

NCFET

PiezoFET BisFET MITFET

SpinFET

ASL

CSL STT/DW

SMG

STOlogic

SWD

NML

Charge vs. Resistance

Larger energy*delay

Smaller energy*delay

Spintronics = more charge, less resistance

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 2

10 3

10 4

10 5

10 6

10 1

10 2

10 3

10 4

10 5

10 6

10 7

Resistance, Ohm

Ca

pa

cit

an

ce

, a

F

CMOS HP

CMOS LP

HomJTFET HetJTFET

gnrTFET ITFET

GpnJ

FEFET NCFET

PiezoFET

BisFET

MITFET SpinFET

ASL

CSL STT/DW

SMG

STOlogic

SWD

NML

Capacitance vs. Resistance

Slower devices

Faster devices

Spintronics = high capacitance hurts speed

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 3

10 4

10 5

10 6

10 7

10 8

10 3

10 4

10 5

10 6

10 7

10 8

Q 2 R, h

En

erg

y*d

ela

y,

h

CMOS HP

CMOS LP

HomJTFET

HetJTFET gnrTFET

ITFET

GpnJ

FEFET

NCFET

BisFET

MITFET

PiezoFET

SpinFET

ASL CSL

STT/DW

SMG

STTtriad

STOlogic

SWD

NML

Energy*Delay vs. Q2*R

ME and FE switch slower than charging

Static Q2R good predictor for dynamic

energy*delay

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


3. Spintronic circuits, layout, area.

Layout pictures, estimates of area, length of

interconnects.


Inverter FO4 and NAND2

Main building blocks. Factors verified against a circuit simulator (e.g. PETE) Include a short interconnect and the next stage to drive. Ctot = total driven cap • NOR same estimate as

NAND • Also need NAND3

IVCft ddtottel

2

ddtotEel VCfE

Switching time

Switching energy

C 4C

Cic

C

Cic

C C

2C

2C


Transistor Based Circuits - 1

icsenaninvse tLttt 21 32

icramnaninvse ELEEE 243 21

icraminvram tLtt 12

icraminvram ELEE 13

XOR

State element

Memory cell

icxornanxor tLtt 23

icxornanxor ELEE 24

Sw. time

Sw. energy

Interconnect length


http://en.wikipedia.org/wiki/File:XOR_from_NAND.svg

Transistor Based Circuits - 2

icmuxinvnannanmux tLtttt 134

icmuxinvnannanmux ELEEEE 134 24

icaddnanxoradd tLttt 121 2/52/3

icaddnanxoradd ELEEE 121 210/78/7

Mux

1 bit of a full adder


Elliptic Spin Torque Majority Gate (STMG)

+V +V Iout -V

GND

CoFe

MgO

Ta

A

B C A B C Out

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

OR

AND

3 inputs and one output having their own fixed layers. Common free layer magnetization switched according to the majority of inputs. This state is sensed by resistance in output

[Electric interface like STTRAM]


Adder: Transistor or Majority Gates

Adder = 28 transistors (at least)

… or just 3 majority gates (Nanomagnetic Logic)

… or just 2 majority gates (All Spin Logic)

… or just 1 majority gate (Spin Wave Devices) !

• Spintronics does logic more efficiently


Majority Gate Circuits - 1

0

A

B

In

In Sto re

icinvramse tLttt 1int

icinvramse ELEEE 1int

icnannan tLtt 2int2

icnannan ELEE 2int2 3

NAND2

State element

Memory cell MEcell

FMwire

Out

Out

Out



A

0 0 1

notA B

B

notB A

Out 12 12 invnanxor ttt

123 invnanxor EEE

Mux

XOR

2:1 mux, need to cascade 3

12 24 invnanmux ttt

12 39 invnanmux EEE



icaddnanmgcadd tLtMt 121

icaddnanmgadd ELEME 121 2

majority gates on critical path

majority gates total

1 bit of a full adder

B

notSum

Cin

notCin A

B

A

Cout

Cin

Sum

B

notSum

Cin

notCin A

B

A

Cout

Cin

Sum

x32


Design Rules and Layout Estimation

Scalable CMOS design rules in terms of l = maximum mask

misalignment. Lithography related. Linked to the minimum feature size, e.g. F=15nm (aka the technology node parameter). Rules and this layout remain the same between process generations (=nodes).


CMOS transistor size

Intel Transistor Pitch vs. “F”

Moore’s law

Contacted gate pitch = 8 l = 4F. Fulfilled for many process generations. Minimum pitch of electrodes, 4F, determine the devices density (not the size of intrinsic devices)


Color Legend for Layout


P-diffusion

N-diffusion

N-well

Poly

Via 1

Metal 1

Via 2

Metal 2

Graphene

Graphene,

top layer

Gate oxide

Graphene

separator

Gate

underlap Ferromagnet

FM inverter

Anisotrop.

ferromagnet Ferromagnet 2 Spin Hall wire

Circuit Layout

Tunneling FET, NAND2

Spin majority gate, 1-bit full adder

Spintronic circuits can be more compact


4. Types of spintronic devices.

Overview of SpinFET, Spin torque domain walls, mLogic, All-spin logic, Charge-spin logic, Spin

majority gate, Spin torque oscillator logic, Nanomagnet logic, Spin wave devices


Tunneling FET

HomJTFET

HetJTFET

gnrTFET

(+) Higher subthreshold slope => smaller supply voltage. (-) Smaller on-current than MOSFET.


Bipolar pseudoSpintronic = BiSFET

(+) Claims of low voltage operation. (-) No room temperature Bose Einstein condensate observed.

Electrons and holes Excitons Exciton condensate Collective tunneling through an oxide must be much stronger Charge imbalance destroys it


Graphene p-n Junction

(+) Promises to switch with small voltage. (-) Practical implementation of reflection struggles.

Graphene electrostatically doped by p or n carriers Electrons reflect in interface dep. On angle Routs electrons by total internal reflection Mux configuration


Spin FET

(+) Switch magnetization for better off-current, reconfigurability. (-) For benchmarked circuits, the spin functionality not used.

Magnetic source and drain Spin polarized carriers might not have vacant states Parallel magnetizations = smaller R Anti-parallel = larger R


All Spin Logic

(+) Good unidirectionality predicted. (-) Problem of spin relaxation = short interconnect.

spin-current

spin-torque

e

e

Spin polarized electrons injected from nanomagnets Spin polarized current by diffusion It switches nanomagnets by spin torque


Charge-Spin Logic

(+) Charge current rather than spin current is conducted. (-) Dipole coupling might be weak.

Current from previous stage switches magnet by spin Hall effect Right magnet is switched by dipole coupling TMR determines the direction of current out


Domain Wall Logic

(+) Good scheme for cascading. (-) Magnetoresistance small for current switching.

Currents summed and injected through side electrodes Domain wall moves and changes magnetoresistance under central electrode


Spin Majority Gate

(+) Higher subthreshold slope => smaller supply voltage. (-) Smaller on-current than MOSFET.

Similar to spin torque memory Currents through nanopillars aim to switch magnetization in the bottom (“free”) layer Majority wins!


Spin Torque Oscillators

(+) Frequency modulation robust. (-) Harder to read off oscillating signal.

Spin torque causes magnetization to precess in a periodic orbit. Several oscillators synchronize determine the frequency of the output


Spin Wave Devices

(+) Uses amplitude and phase, ingenious design of circuits. (-) Need precise phasing of signals.

Ac current causes input magnetization oscillate Magnetization oscillation propagates as a spin wave Pulses of spin waves switch output magnets


Nano-Magnet Logic

(+) Relatively fast switching from unstable state. (-) Dipole interactions between magnets sensitive to shape.

Magnetic fields set nanomagnets in an unstable state Dipole interactions between them flip magnetization Magnetization read off by magnetoresistance


5. Estimates for switching speed and energy

Building up estimates for more complicated

circuits from simpler using section 3. Calculating power dissipation, and computation

throughput. Take-away messages.


10 1

10 2

10 3

10 4

10 5

10 6

10 -1

10 0

10 1

10 2

Delay, ps

En

erg

y,

fJ

CMOS HP

CMOS LP

HomJTFET

HetJTFET

gnrTFET ITFET

GpnJ FEFET

NCFET

BisFET

MITFET

PiezoFET

SpinFET

ASL

CSL

STT/DW

SMG

STTtriad STOlogic

SWD

NML

32bit adder

Energy vs. Delay , Circuit

Spin torque

Transistors

10-26

10-25

10-24 10-23 10-22 10-21

E*d

Magnetoelectric

Ferroelectric

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic

Slower, but non-volatile


Arithmetic Logic Unit

32 latch

32 latch

32 latch

32 AO

32 RF

32 RF

Clk0

Clk1 icaomuxaddxorseao tLttttt 32

icaomuxxorseaddao ELEEEEE 223232

icaluseaoalu tLttt 2

icaluramseaoalu ELEEEE 32

=one clock cycle

Arithmetic operation (AO)

Overall ALU

32 NAND

32 NOR

32 ADD ER 32

XOR

A

32 MUX

Ctrl1

Ctrl0

B


10 2

10 3

10 4

10 5

10 6

10 0

10 1

10 2

10 3

10 4

Clock Period, ps

En

erg

y, f

J

CMOS HP

CMOS LP

0.3V HomJTFET

HetJTFET

gnrTFET ITFET

GpnJ FEFET

NCFET

PiezoFET

BisFET MITFET

SpinFET

ASL

CSL STT/DW

SMG

STOlogic

SWD

NML

32bit ALU

Energy vs. Delay

Tunneling

Ferroelectric

Spin Torque

Magneto electric

Ferroelectric – faster non-volatile

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 -1

10 0

10 1

10 2

10 3

10 4

10 1

10 2

10 3

Device Delay, ps

Ad

de

r/D

evic

e D

ela

y

CMOS HP CMOS LP

HomJTFET

HetJTFET gnrTFET ITFET

GpnJ

FEFET NCFET

PiezoFET

BisFET MITFET

SpinFET

ASL CSL

STT/DW SMG

STOlogic

SWD

NML

Device vs. Circuit, Time

Majority gates

Majority gates => faster circuits

Fast devices

Fast

cir

cu

its

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 -3

10 -2

10 -1

10 0

10 1

10 2

10 3

Device Energy, fJ

Ad

der/

Devic

e E

nerg

y

CMOS HP

CMOS LP HomJTFET

HetJTFET

gnrTFET

ITFET GpnJ

FEFET

NCFET

PiezoFET

BisFET

MITFET

SpinFET

ASL CSL

STT/DW

SMG STOlogic

SWD

NML

Device vs. Circuit, Energy

Low energy devices

Lo

w e

nerg

y

cir

cu

its

More devices (STT/DW, STOlogic) => higher energy circuits

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


10 -4

10 -2

10 0

10 2

10 4

10 3

10 4

10 5

Devics E*d, fJ × ps

Ad

de

r/D

evic

e E

*d

CMOS HP CMOS LP

HomJTFET HetJTFET

gnrTFET ITFET

GpnJ

FEFET NCFET

PiezoFET

BisFET MITFET

SpinFET

ASL

CSL

STT/DW

SMG STOlogic

SWD

NML

Device vs. Circuit, Energy*Delay

Fewer elements => efficient circuits

Efficient devices

Eff

icie

nt

cir

cu

its

CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic


Energy Aware Figure of Merit: Throughput with Capped Power

New FOM = Throughput with Capped Power

“Computational throughput with capped power measured as Operations per second per logic die area measures how useful a computer is, in a power constrained computing environment.”

Choose 10W/cm2* as the cap

Re-scales throughput by the same factor, either

i. Less dense circuits

ii. Slower circuits

* Clocking and long interconnect dissipation are not included

Throughput @ Capped Power = Switching Operations/Area/Time

T@CP Units = [Operations/s/cm2]


10 0

10 1

10 2

10 3

10 -1

10 0

10 1

Throughput, TIOPS/cm 2

Po

wer,

W/c

m 2

CMOS HP

CMOS LP

0.3V

HomJTFET

HetJTFET

gnrTFET

ITFET GpnJ

FEFET

NCFET

PiezoFET

BisFET

MITFET

SpinFET

ASL

CSL

STT/DW

SMG

STOlogic

SWD

NML

32bit ALU

Throughput vs. Capped Power CMOS ref

Electronic

Spintronic

Ferroelectric

Orbitronic

Straintronic

Tunneling

Ferroelectric

Spin Torque

Magneto electric

TFET look outstanding on throughput, ME on power

Cap=10W/cm2

TIOPS = terra integer

operations per second


Insights of Benchmarking Practical considerations

1. Area is determined by metal pitch (4F) to connect to the device [terminal connections]

2. Majority gates permit more compact, faster circuits

3. Power delivery dominates for very low-voltage devices

Results

1. Spintronics devices are dominated by either – switching energy (spin torque)

– magnetization switching speed (magnetoelectric).

2. Charge-based devices are an attractive option: good E*d, compatible with CMOS circuits

3. Spintronic devices still competitive on throughput at low power


Acknowledgements

Researchers in NRI:

J. Allen, M. Baldo, B. Behin-Aein, G. Csaba, J.A. Currivan,

S. Datta, S. Datta, K. Galatsis, Y. Gao, S. Hu, A. Khitun,

A.Kozhanov, I. Krivorotov, J. Lee, M. Lundstrom, A. MacDonald,

D.Markovic, A. Naeemi, V. Narayanan, M. Niemier, C. Pan,

W. Porod, K. Roy, L. F. Register, C. Ross, S. Salahuddin,

V. Saripalli, A. Sarkar, A. Seabaugh, S. Srinivasan, K. Bernstein,

and J. Welser

Colleagues at Intel:

G. Bourianoff, B. Doyle, C. Kuo, U. Avci, R. Kim, S. Manipatruni,

A. Raychowdhury, C. Augustine


References

D. Nikonov and I. Young, Proceedings of IEDM, 25.4 (2012)

D. E. Nikonov and I. A. Young, Proceedings of IEEE v. 101, pp. 2498 - 2533 (2013).

Apologies if the work was not cited properly, see references in the above papers


Benchmarking Spintronic Logic Devices

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