Verilog-A LanguageVerilog-A Language

ByBy

William VidesWilliam Vides

Modfied by George EngelModfied by George Engel

Difference between Digital Difference between Digital and Analog Designand Analog Design

Always @ (enable) beginvalid = 1’b0;// do write cycleaddr_lines = addr;data_lines = data; @ (negedge clk) begin valid = 1’b1; endend Top DownRefined from HDL

LevelBottom-UpTransistor level

Behavioral

Gate

Switch

Circuit

Higher levelof abstraction

Verilog-A as an extension Verilog-A as an extension of Spiceof Spice

Analog System Description Analog System Description and simulationand simulation Structural DescriptionStructural Description

• a module is comprised of other child modulesa module is comprised of other child modules Behavioral DescriptionBehavioral Description

• descriptions in a programmatic fashion with the descriptions in a programmatic fashion with the Verilog-A languageVerilog-A language

• The module is defined in terms of the values for The module is defined in terms of the values for each signaleach signal

Mixed-level DescriptionsMixed-level Descriptions• Combine both Structural and Behavioral Combine both Structural and Behavioral

DescriptionsDescriptions

Modem ExampleModem Example

modem

modulator channel demodulator

The modem system is made up of 1) the modulator2) a channel3) the demodulator

Structural Description Structural Description hierarchyhierarchy

Module: qam

Instance: modmodule: qam_mod

Instance: c1module: channel

Instance: demodmodule: qam_demod

Structural Description of Structural Description of the Modem Systemthe Modem System

// Verilog A definition of the modem System`include “std.va”

module modem( dout, din)’ inout dout, din; electrical dout, din;parameter real fc = 100.0e6;

electrical clk, cin, cout;qam_mod #(.carrier_freq(fc)) mod (cin,din,clk);channel c1 ( cout, cin);qam_demod #(.carrier_freq(fc)) demod (dout,cout,clk);endmodule

Structural DescriptionStructural Description

Type of module instance Name of the instance created

qam_mod # ( .carrier_freq(fc)) mod ( cin, din, clk);

Parameter name in child ( qam_mod) module assigned as: carrier_freq = fc

16_QAM modem Example16_QAM modem Example

2-bitd2a

Serin_parout

2-bitd2a aq

A sin( 2pi fct + pi/ 4)

di

dq

aiA cos( 2 pi fct + pi/4)

din mout

A(t)cos( 2pifct +0(t))

Verilog A mixed Signal Verilog A mixed Signal definitiondefinitionof 16-QAM modulatorof 16-QAM modulator

module qam_mod( mout, din, clk); inout mout, din, clk; electrical mout, din, clk; parameter real fc = 100.0e6; electrical di1,di2, dq1, dq2; electrical ai, aq; serin_parout sipo( di1,di2,dq1,dq2,din,clk); d2a d2ai(ai, di1,di2,clk); d2a d2aq(aq, dq1,dq2,clk); real phase;

Verilog A mixed Signal Verilog A mixed Signal definitiondefinitionof 16-QAM modulatorof 16-QAM modulator

analog begin phase = 2.0 * `M_PI * fc* $realtime() + `M_PI_4; V(mout) <+ 0.5 * (V(ai) * cos(phase) + V(aq) * sin (phase));endendmodule

The behavioral definition of the QAMmodulation is defined

The signals ai and aq are the outputs of the 2-bit D/A converters

Type of analog systemsType of analog systems

Conservative SystemsConservative Systems• use of Kirchoff’s lawsuse of Kirchoff’s laws• Electrical Systems use KVL and KCLElectrical Systems use KVL and KCL• Any conservative System use KPL and KFLAny conservative System use KPL and KFL

– applied to branchesapplied to branches

Signal Flow SystemsSignal Flow Systems• only potential is associated with every nodeonly potential is associated with every node• unidirectionalunidirectional• notion of ports ( input / output)notion of ports ( input / output)

Conservative SystemsConservative Systems

Device

+ -V

In a conservative system the charges or signals can enter a particular device in both ways.

Signal Flow SystemsSignal Flow Systems

in OutAmplifier

In signal flow systems a signal can only enter a devicein one way only.

What is Simulation?What is Simulation?

simulation is a process in which a simulation is a process in which a system of nonlinear ordinary system of nonlinear ordinary differential equations is solveddifferential equations is solved

this equations are not input this equations are not input directly , but derived from each of directly , but derived from each of the models that are interconnected the models that are interconnected in the netlistin the netlist

What it means to the What it means to the user ?user ?

To the user a simulation is essentially a To the user a simulation is essentially a software version of an oscilloscope or software version of an oscilloscope or logic analyzer.logic analyzer.

A simulation is a technique by which the A simulation is a technique by which the user ask questions and receives user ask questions and receives answers from a program .answers from a program .

The quality of the answers depends on The quality of the answers depends on the quality of the questions.the quality of the questions.

Analog System SimulationAnalog System Simulation

The Standard approach to analog circuit The Standard approach to analog circuit simulation involvessimulation involves• formulate the differential-algebraic equations formulate the differential-algebraic equations

for the circuitfor the circuit• applying implicit integration methods to the applying implicit integration methods to the

sequence of nonlinear algebraic equationssequence of nonlinear algebraic equations• iterative methods such as Newton-Raphson iterative methods such as Newton-Raphson

to reduce to a set of linear equationsto reduce to a set of linear equations• using sparse matrix techniques to solve the using sparse matrix techniques to solve the

linear equationslinear equations

Analog Model PropertiesAnalog Model Properties

The Verilog-A language can be The Verilog-A language can be used to represent different types used to represent different types of behaviors these includeof behaviors these include• LinearLinear• NonlinearNonlinear• Piecewise linearPiecewise linear• Integro differentialIntegro differential• Event-driven AnalogEvent-driven Analog

Analog OperatorsAnalog Operators

The Verilog-A language defines The Verilog-A language defines analog operators for analog operators for • Time DerivativeTime Derivative• Time IntegralTime Integral• Linear time delayLinear time delay• Discrete waveform filtersDiscrete waveform filters• LaPlace Transform filtersLaPlace Transform filters• Z-transform filtersZ-transform filters

Time Derivative OperatorTime Derivative Operator

The ddt Operator computes the The ddt Operator computes the time derivative of its argumentstime derivative of its arguments• ddt ( expression)ddt ( expression)

In DC analysis the ddt operator In DC analysis the ddt operator returns a zero.returns a zero.

Application of the ddt operator Application of the ddt operator results in a zero at the origin.results in a zero at the origin.

Time Integral OperatorTime Integral Operator

The idt operator computes the time The idt operator computes the time integral of its argumentsintegral of its arguments• idt( expression, ic, reset)idt( expression, ic, reset)

When specified with initial conditions When specified with initial conditions the idt operator returns the value of the idt operator returns the value of the initial condition in DC.the initial condition in DC.

Without initial conditions , idt Without initial conditions , idt multiplies its argument by infinity in multiplies its argument by infinity in DC analysis.DC analysis.

Time Integral OperatorTime Integral Operator

The Optional argument RESET The Optional argument RESET allows resetting of the integrator to allows resetting of the integrator to the initial condition or IC value.the initial condition or IC value.

Application of the idt operator Application of the idt operator results in a pole at the origin.results in a pole at the origin.

Delay OperatorDelay Operator

Delay operator implements a Delay operator implements a transport or linear time delay for transport or linear time delay for continuous waveformscontinuous waveforms• delay ( expression, dt)delay ( expression, dt)

The parameter DT must be positiveThe parameter DT must be positive The effect of the delay operator in The effect of the delay operator in

the time domain is to provide a the time domain is to provide a direct time translation of the inputdirect time translation of the input

Transition OperatorTransition Operator

The transition operator smooths out The transition operator smooths out piece-wise constant waveforms. piece-wise constant waveforms.

The transition filter is used to imitate The transition filter is used to imitate transitions and delays on discrete transitions and delays on discrete signalssignals• transition ( expression, dt, tr, tf)transition ( expression, dt, tr, tf)

The input expression to the transition The input expression to the transition operator must be defined in terms of operator must be defined in terms of discrete states.discrete states.

Transition OperatorTransition Operator

The parameters dt, tr, tf are optionalThe parameters dt, tr, tf are optional• tr - transition risetr - transition rise• tf - transition falltf - transition fall• dt - change in timedt - change in time

if dt is not specified then it is taken to if dt is not specified then it is taken to be zerobe zero

if the value for tr is specified the if the value for tr is specified the simulator will use it for both the rise simulator will use it for both the rise and fall times.and fall times.

Transition OperatorTransition Operator

When rise and fall times are longer When rise and fall times are longer than the specified delaythan the specified delay• if the new final value level is below if the new final value level is below

the current value the transition the current value the transition Operator uses the old destination as Operator uses the old destination as the origin.the origin.

• If the new destination is above the If the new destination is above the current level the first origin is current level the first origin is retainedretained

Transition OperatorTransition Operator

Translated Origin Old value

New value

Old origin tr

tf

Input change

A rising transition is interrupted near its midpoint, and the new destination level of the value is below the current value. For thenew origin and destination. The transition computes the slope that completes the transition from origin in the specified transition time. It then uses the computed slope to transition from the current value to the new destination.

Slew OperatorSlew Operator

The slew operator bounds the The slew operator bounds the slope of the waveformslope of the waveform

used to generate continuous used to generate continuous signals from piece-wise continuous signals from piece-wise continuous signalssignals• slew ( expression, mpsr, mnsr)slew ( expression, mpsr, mnsr)• mpsr - maximum positive slew ratempsr - maximum positive slew rate• mnsr - minimum negative slew ratemnsr - minimum negative slew rate

Slew OperatorSlew Operator

The Slew Operator forces all transitions of The Slew Operator forces all transitions of the input expression faster than mpsr to the input expression faster than mpsr to change at mpsr for positive transitions change at mpsr for positive transitions and limits negative transitions to mnsrand limits negative transitions to mnsr

mpsr must be greater than zerompsr must be greater than zero mnsr must be lower than zeromnsr must be lower than zero if only one rate is specified, the absolute if only one rate is specified, the absolute

value will be used for both ratesvalue will be used for both rates

Slew OperatorSlew Operator

If no rate is specified the slew operator If no rate is specified the slew operator passes the signal through unchanged.passes the signal through unchanged.

In DC analyses, the slew operator passes In DC analyses, the slew operator passes the value of the destination to its outputthe value of the destination to its output

In AC small-signal analyses the slew In AC small-signal analyses the slew function has unity transfer function function has unity transfer function • except when slewing, in that case it has zero except when slewing, in that case it has zero

transmission through the slew operatortransmission through the slew operator

Laplace Transform Laplace Transform OperatorsOperators

The Laplace transform operators The Laplace transform operators implement lumped, continuous-time implement lumped, continuous-time filtersfilters• laplace_zp(express, numerator, denominator)laplace_zp(express, numerator, denominator)• lapace_zd(express, numerator,denominator)lapace_zd(express, numerator,denominator)• lapace_np( express, numerator,denominator)lapace_np( express, numerator,denominator)• lapace_nd(express, numerator,denominator)lapace_nd(express, numerator,denominator)

– H(s) = N(s)/D(s)H(s) = N(s)/D(s)

Laplace Transform Laplace Transform OperatorOperator

The laplace transform analog operator The laplace transform analog operator take vector arguments that specify the take vector arguments that specify the coefficients of the filtercoefficients of the filter

Laplace analog operators represent Laplace analog operators represent linear time-Invariant filters linear time-Invariant filters

laplace_zp - the zeros and poles are laplace_zp - the zeros and poles are specified as pairs of real numbersspecified as pairs of real numbers• specifying the real and imaginary specifying the real and imaginary

components of each zero or polecomponents of each zero or pole

Laplace Transform Laplace Transform OperatorOperator

Laplace_nd - zeros and poles of the Laplace_nd - zeros and poles of the filter are specified as polynomial filter are specified as polynomial coefficients from lowest order term to coefficients from lowest order term to highesthighest

Laplace_zd - zeros of the filter are Laplace_zd - zeros of the filter are specified as pairs of real numbers and specified as pairs of real numbers and the poles of the filter are specified as the poles of the filter are specified as polynomial coefficients polynomial coefficients

Laplace Transform Laplace Transform OperatorOperator

Laplace_np - Zeros of the filter are Laplace_np - Zeros of the filter are specified as polynomial coefficients specified as polynomial coefficients and the poles of the filter are and the poles of the filter are specified as pairs of real numbersspecified as pairs of real numbers

Laplace Transform Laplace Transform exampleexample

// Laplace analog operator example of Butterworth low-pass// filter using laplace_ndmodule laplace_op(out , in); inout out, in; electrical out, in;

analog V(out) <+ laplace_nd ( V(in), {1.0}, {1.0, 3.236, 5.236, 5.236, 3.236, 1.0});endmoduleTaken from the equation H(s) = 1/( s^5 + 3.236s^4 +5.236s^3 +5.236s^2 +3.236s +1)

Z-Transform OperatorsZ-Transform Operators

The Z-Transform operators implement The Z-Transform operators implement linear discrete-time filterslinear discrete-time filters• zi_zp( expression, numerator,denominator,T zi_zp( expression, numerator,denominator,T

,trf ,t0) ,trf ,t0)• zi_zd( expression, numerator,denominator,T zi_zd( expression, numerator,denominator,T

,trf ,t0) ,trf ,t0)• zi_np( expression, numerator,denominator,T zi_np( expression, numerator,denominator,T

,trf ,t0) ,trf ,t0)• zi_nd( expression, numerator,denominator,T zi_nd( expression, numerator,denominator,T

,trf ,t0) ,trf ,t0)

Z-Transform OperatorsZ-Transform Operators

• H( z ) = N( z )/ D( z )H( z ) = N( z )/ D( z ) the Z-transform analog operator the Z-transform analog operator

take vector arguments that take vector arguments that specify the coefficients of the filter.specify the coefficients of the filter.

All Z-transform share the All Z-transform share the arguments T, trf, and t0arguments T, trf, and t0• T -specifies the period of the filterT -specifies the period of the filter

– mandatory and must be positivemandatory and must be positive

Z-Transform OperatorsZ-Transform Operators

• Trf - specifies the optional transition Trf - specifies the optional transition time and must be positivetime and must be positive– if trf is zero, then the output is abruptly if trf is zero, then the output is abruptly

discontinuousdiscontinuous– a Z-transform filter with zero transition time a Z-transform filter with zero transition time

assigned directly to a source branch can assigned directly to a source branch can generate discontinuitiesgenerate discontinuities

• t0 - specifies the time of the first t0 - specifies the time of the first transition and is optionaltransition and is optional– if t0 is not given, the transition occurs at t=0if t0 is not given, the transition occurs at t=0

Z-Transform OperatorsZ-Transform Operators

Zi_zp - zeros and poles of the filter are Zi_zp - zeros and poles of the filter are specified as pairs of real numbersspecified as pairs of real numbers• specifying the real and imaginary specifying the real and imaginary

components of each zero or polecomponents of each zero or pole

zi_nd- zeros and poles of the filters are zi_nd- zeros and poles of the filters are specified as polynomial coefficientsspecified as polynomial coefficients• from the lowest order term to the highestfrom the lowest order term to the highest

Z-Transform OperatorsZ-Transform Operators

Zi_zd - zeros of the filter are specified Zi_zd - zeros of the filter are specified as pairs of real numbers and the poles as pairs of real numbers and the poles of the filter are specified as polynomial of the filter are specified as polynomial coefficients coefficients

zi_np- zeros of the filters are specified zi_np- zeros of the filters are specified as polynomial coefficients and the as polynomial coefficients and the poles of the filter are specified as pairs poles of the filter are specified as pairs of real numbersof real numbers

Capacitor MacromodelCapacitor Macromodel// capacitor_macro.va

`include "constants.h"`include "discipline.h"

module capacitor_macro(top, bot); inout top, bot ; electrical top, bot ; parameter real C = 1p ;

analog begin I(top,bot) <+ C * ddt(V(top, bot)) ;endendmodule

Resistor MacromodelResistor Macromodel

// resistor_macro.va`include "discipline.h"`include "constants.h"

module resistor_macro(a,b); inout a,b; electrical a,b; branch(a,b) res; parameter real R=10K;

analog begin I(res) <+ V(res) / R ; end

endmodule

Common Emitter amplifier Common Emitter amplifier with RC bandpass filter with RC bandpass filter ExampleExample

gain =25.0n1

R1

R2

C2

C1

Vin Vout

gnd

Verilog A behavioral Verilog A behavioral description of ce-amp with description of ce-amp with RC bandpass filterRC bandpass filter

module mbce_amp_rcn ( in, out, gnd); inout in, out, gnd; electrical in, out, gnd;

parameter real gain = 1.0; parameter real r1 = 4k; parameter real c1 = 100n; parameter real r2 = 100k; parameter real c2 = 2.8p;

electrical n1, n2;

Verilog A behavioral Verilog A behavioral description of ce-amp with RC description of ce-amp with RC bandpass filterbandpass filter

analog begin I( in, n1) <+ c1 * ddt( V(in,n1)); V(n1, gnd) <+ r1 * I(in,n1); I(n1,n2) <+ V(n1, n2) / r2; I(n2,gnd) <+ c2* ddt( V(n2, gnd)); V(out, gnd) <+ V(n2,gnd) * (-gain); end

endmodule

Switch Switch MacromodelMacromodel

// ideal switch

`include "disciplines.h"`include "constants.h"

module sw_macro(ctl, inp, outp); inout inp, ctl, outp ; electrical inp, ctl, outp ;

parameter real Vth=2.5 from (0:5) ; parameter real Ron = 1k from (0:inf) ; parameter real Roff = 1e12 from (0:inf) ; parameter real tr=100p from [0:inf) ; parameter real tf=100p from [0:inf) ;

real Rch ;

Switch Macromodel Switch Macromodel (2)(2)

analog begin if (analysis("static")) begin

Rch = Roff ; end else begin if (V(ctl) < Vth) Rch = Roff ; else Rch = Ron ; end; I(inp, outp) <+ V(inp, outp) / transition(Rch,0, tr, tf) ; endendmodule

CSA CSA MacromodelMacromodel

//// csa_macro //`include "discipline.h"`include "constants.h"

module csa_macro(inp, lo_gain, csa_gnd, outp) ; inout inp, outp, lo_gain, csa_gnd ; electrical inp, outp, lo_gain, csa_gnd ;

CSA CSA Macromodel (2)Macromodel (2)

parameter real gm_lo = 2.4e-3 ; parameter real gm_hi = 12e-3 ; parameter real Gf_lo = 500e-9 ; parameter real Gf_hi = 100e-9 ; parameter real Cf_lo = 12.5e-12 ; parameter real Cf_hi = 2.5e-12 ; parameter real Cfl_lo = 14e-12 ; parameter real Cfl_hi = 3e-12 ; parameter real Ct_lo = 95e-12 ; parameter real Ct_hi = 85e-12 ; parameter real b0_lo = gm_lo * Gf_lo ; parameter real b0_hi = gm_hi * Gf_hi ; parameter real b1_lo = gm_lo * Cf_lo ; parameter real b1_hi = gm_hi * Cf_hi ; parameter real b2_lo = Ct_lo * Cfl_lo ; parameter real b2_hi = Ct_hi * Cfl_hi ; parameter real Vtp = 0.75 ; parameter real Vdss = 0.48546 ;

real Vin0, Vin1, vos ;

CSA CSA Macromodel (3)Macromodel (3)

analog begin @(initial_step) begin

vos = V(csa_gnd) - Vtp - Vdss ; end ;

if (analysis("static")) begin vos = V(csa_gnd) - Vtp - Vdss ; Vin0 = vos ; Vin1 = vos ; V(outp) <+ vos ;

end

CSA CSA Macromodel (4)Macromodel (4)

else begin Vin0 = vos + 0.9 * laplace_nd(I(inp), {-1 * gm_hi, 0, 0} ,

{b0_hi, b1_hi, b2_hi}) ;

Vin1 = vos + 0.9 * laplace_nd(I(inp), {-1 * gm_lo , 0, 0} ,

{b0_lo, b1_lo , b2_lo}) ;

if (V(lo_gain) == 0) V(outp) <+ Vin0 ;

else V(outp) <+ Vin1 ;

end; endendmodule