MODFIED GLITCH-FREE AND CASCADABLE ADIABATIC LOGIC...
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MODFIED GLITCH-FREE AND CASCADABLE ADIABATIC LOGIC CIRCUITS Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science (by Research) in VLSI by Prashanth Paramahans M. 200742003 [email protected] International Institute of Information Technology Hyderabad,India June -2010
Transcript of MODFIED GLITCH-FREE AND CASCADABLE ADIABATIC LOGIC...
MODFIED GLITCH-FREE AND CASCADABLE ADIABATIC LOGIC CIRCUITS
Thesis submitted in partial fulfillmentof the requirements for the degree of
Master of Science (by Research)in
VLSI
byPrashanth Paramahans M.
International Institute of Information TechnologyHyderabad,India
June -2010
INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGYHyderabad, India
CERTIFICATE
It is certified that the work contained in this thesis titled “Modified Glitch-Free and Cascadable Adiabatic Logic Circuits” by Prashanth Paramahans , has been carried out under my supervision and has not been submitted elsewhere for a degree
____________ _______________________________Date Advisor: Professor Satyam Mandavilli
Acknowledgement
I would like to thank my advisor , Prof. M Satyam for his support,guidance , motivation, and immense knowledge which played a greatrole during the development of ideas in the thesis.I could not haveimagined having a better advisor and mentor for my Master’s study.Ithank my fellow labmates in CVEST for the stimulating discussions wehad,and for all the fun we have had in the last few years.
Last but not the least, I would like to thank my family for theircontinued support through out my study.
Abstract
Conventional CMOS logic circuit design approaches rely on chargingthe output capacitive nodes to the power supply Vdd or dischargingit to ground.This design approach has been widely used.For Lowpower applications, although there are many techniques both at cir-cuit level and system level, a very fundamental source of energydissipation is the discharge of the capacitor to ground.Every timea capacitor is discharged to ground, an amount of energy = 1
2CV 2
stored in the capacitor is lost.This loss of energy can be preventedif instead of discharging the capacitor to ground,the charge or en-ergy stored can be recycled. Another way of reducing the powerconsumption is to design the circuit in such a way that the charg-ing of the capacitive node takes place very slowly.It has been ob-served that slowly charging the capacitor requires lesser energy thanabrupt charging.Adiabatic circuits use the above two methods viz.slow charging and discharging, and charge recycling to minimizethe power consumed.Several Adiabatic designs have been proposedin literature.Most of them achieve significant power savings in com-parision to conventional circuits.Drawbacks of these circuits includecomplex circuit design for achieving simple operations,requirementof multiple clocks and/or requirement of complimentary input sig-nals for controlling the charging/discharging process.The Currentwork is based on an existing adiabatic logic style known as GF-CAL (Glitch Free and Cascadable Adiabatic Logic )which is simpleand doesnt require complimentary signals or complex clocking.TheGFCAL has a drawback that it uses junction diodes for controllingthe charging and discharging of output nodal capacitance.Junctiondiodes are difficult to fabricate in a CMOS process and they are re-sponsible for power dissipation due to the cut-in voltage drop acrossthem.
This work improves the circuit by replacing the diodes with tran-sistors that control the charging and discharging process.The effi-ciency has gone up from 50% for GFCAL to about 60% for the mod-ified circuit in comparison to conventional CMOS logic circuits.Themodified design is found to work satisfactorily, is cascadable andsimple block level implementations like adders have been demon-strated and verified to work with lower power consumption thanconventional CMOS circuits.
Contents
Chapter 1. Basics of Low Power Design . . . . . . . . . . . . . . . . . 3
Need for Low-Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1. Sources of Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 41.2. Low Power Design techniques . . . . . . . . . . . . . . . . . . . . . 4
1.2.1. Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . 51.2.2. Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . 6
1.3. Active power Reduction . . . . . . . . . . . . . . . . . . . . . . . . 71.3.1. Activity Reduction . . . . . . . . . . . . . . . . . . . . . . . 71.3.2. Supply voltage reduction . . . . . . . . . . . . . . . . . . . . 7
1.4. Leakage reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4.1. Leakage reduction using dual Vt technology . . . . . . . . . 81.4.2. Stacking technique . . . . . . . . . . . . . . . . . . . . . . . 91.4.3. Supply gating . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4.4. System and architecture level power reduction . . . . . . . 9
1.5. Adiabatic or charge recovery based circuit design . . . . . . . . . . 10
Chapter 2. Adiabatic Architectures . . . . . . . . . . . . . . . . . . . . 11
2.1. RC circuits and related Energetics . . . . . . . . . . . . . . . . . . . 112.2. Previous Adiabatic Circuit techniques . . . . . . . . . . . . . . . . . 13
2.2.1. Adiabatic Dynamic Logic (ADL) . . . . . . . . . . . . . . . 142.2.2. Split Level Charge Recovery Logic (SCRL) . . . . . . . . . 142.2.3. 2N-2P logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.4. 2N2N-2D logic . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.5. Quasi Static Energy Recovery Logic (QSERL) . . . . . . . 172.2.6. Efficient Charge Recovery Logic (ECRL) . . . . . . . . . . . 182.2.7. Glitch-Free and Cascadable Adiabatic Logic (GFCAL) . . . 192.2.8. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 3. Modified GFCAL Logic . . . . . . . . . . . . . . . . . . . . 21
3.1. Operation of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . 213.2. Simulation of the basic transistor based adiabatic inverter . . . . . 233.3. Qualitative discussion on the output waveforms . . . . . . . . . . . 25
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3.4. Effect of variation of Device parameters . . . . . . . . . . . . . . . . 253.4.1. Effect of Variation of transistor widths . . . . . . . . . . . . 253.4.2. Variation with Load capacitance . . . . . . . . . . . . . . . 273.4.3. Varying the clock power Frequency . . . . . . . . . . . . . . 293.4.4. Varying the input data frequency . . . . . . . . . . . . . . . 303.4.5. Delay characteristics and input output relations . . . . . . . 31
3.5. Cascadability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 4. Mathematical model of the adiabatic inverter circuit . 34
4.1. Charging process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.1.1. Energy during charging . . . . . . . . . . . . . . . . . . . . 35
4.2. Discharge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364.2.1. Energy consumed during the discharge cycle . . . . . . . . . 37
4.3. Performance Variation with Circuit Parameters . . . . . . . . . . . 394.4. Efficiency estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 5. Logic design based on MGFCAL . . . . . . . . . . . . . . 43
5.1. NAND function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2. NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.3. Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.1. Estimating the power consumption by simulation . . . . . . 465.4. Further application-an 8-bit adder circuit. . . . . . . . . . . . . . . 485.5. Implementation of sequential blocks using Modified GFCAL gates . 50
5.5.1. A JK Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A. The MOS transistor and CMOS based circuits . . . 55
Appendix B. Linear Feedback Shift register . . . . . . . . . . . . . . 59
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 1
Basics of Low Power Design
Need for Low-Power Design
With increased scaling in CMOS technology, todays designs are capableof performing very high speed computations as the complexity and numberof devices on a given IC is no longer an issue. Much of the research effortsin the recent decades have been dedicated to improving the speed of digitalsystems.Thus, high speed computation has become an expected norm foraverage users.Along with this, there is a growing desire to have access tocomputation at any location without being limited to a given space with awired network.This requirement for portability of the computational deviceplaces restrictions on the size, weight and power.Most of the times, it isobserved that the heaviest component in any such portable system is thebattery.A typical Ni-Cd battery provides only 20 Watt-hours of energy perpound of weight.Battery efficiency has not improved at the same pace as thecomplexity and power requirement of the recently developed designs.
Previously, portability was mostly associated with low throughput deviceslike calculators and wrist-watches.But with the growing use of portable de-vices capable of performing computations comparable to desktop computers,it has become necessary to adopt design methodologies that would work withlow-power and give high throughput.This issue of low power is becoming moreimportant even in non-portable applications where power is available.Untilrecently, these non-portable systems did not have any concern for low powerdue to availability of cooling systems like heat sinks and fans.But with in-creasing device densities, the amount of heat radiated by such systems isincreasing and there is a need to adopt low power design approaches in suchapplications to minimize the amount of heat radiated and to keep the costof cooling systems to a minimum.
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Thus it is evident that methodologies for design of low power systems areneeded.We will examine the sources of power dissipation in digital circuitsand later discuss briefly the existing techniques that are used to achieve lowpower designs.
1.1. Sources of Power Dissipation
The three major sources of power dissipation in CMOS circuits can beexpressed using the equation given below
Ptotal = Pswitching + Pshort−circuit + Pleakage (1.1)
Ptotal = α.V.Vdd.fclk.Cload + Isc.Vdd + Ileakage.Vdd (1.2)
In equation (1.2), the first term represents power dissipation due to switch-ing. V is the voltage swing, Cload is the load capacitance and fclk is theswitching frequency. The factor α is the activity factor which represents thefraction of the circuit that is switching. In most cases the voltage swing forV is same as the supply voltage Vdd in such cases the term V becomes Vdd.The second term in the equation represents short-circuit power dissipationwhich occurs when both the pull-up and pull-down paths in a CMOS circuitare momentarily ON. In such a condition, a short-circuit current Isc flowsfrom Vdd to the ground and causes power dissipation . Apart from thesetwo terms viz. the switching power and short-circuit power, there is alwayspresent the component due to leakage currents. Leakage currents dependupon various fabrication technology related factors like threshold voltage Vth, device dimensions, substrate-injection etc. Previously, a dominant portionof the power dissipated in a CMOS circuit was due to switching and as suchmany techniques for low power design tried to minimize switching, but withadvanced technology nodes,leakage power is becoming a concern in modernIC designs and as such techniques for minimizing the leakage power havebeen developed.
1.2. Low Power Design techniques
Low power design can be attained by either following a circuit basedapproach or an architectural approach or at a higher level where the pro-gramming is optimized.In most cases a combination of one or more of theses
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Figure 1.1. Energy,delay Vs. Voltage
methods is used to optimize the power consumption of a design. At circuitlevel, the main task is to minimize any one of the components of equation1.2.In the following sections a brief discussion on different methods used toobtain low power design are given
For a given technology , the energy per operation can be reduced bylowering the supply voltage.Since capacitance and threshold voltage are stillconstant, the speed of the circuit will be slower.It has been shown in [25]thatdelay is related to the threshold voltage and output capacitance as
td = kCV
(V − Vth)2(1.3)
Figure 1.1 shows a plot of energy-per-operation, delay and energy-delayas the supply voltage is scaled.At large voltages, reducing the supply voltagereduces the energy with very small change in delay.But at voltages near thethreshold voltage of the device , even a small change in supply causes a largechange in delay with modest change in energy. At Vdd = 3Vtha minima isobserved and as such at this point , changing the supply voltage does notaffect the energy-delay product strongly and thus allows for trading delayfor energy.From the point Vdd = 1.5Vth to Vdd = 6Vththere is a factor of 8variation of energy that can be traded for delay without much change in theenergy-delay product.
1.2.1. Transistor Sizing
Power consumption can also be reduced by scaling down the devices in acircuit. Since the capacitance due to gates of the transistors get reduced withreduced dimensions, the power consumed decreases.But the sizing reduces thecurrent drive of the logic gates and thus reduces the speed of operation.Thiscan be understood by taking the example of a chain of inverters. Figure
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Figure 1.2. Energy,Delay Vs. Transistor Width
1.2 shows the delay, energy,Energy-delay of a single stage in the inverterchain as a function of the transistor’s capacitance contribution to the totalload. In case of smaller transistors, the load will be due to load capacitanceof next stage and for larger transistors, the gate capacitance will also bepresent and comprises a major portion of the load capacitance. For smallerdevices, energy is dominated by switching of the load capacitance and delayis inversely related to the device width and as such increasing the transistorwidth improves the energy-delay product.For large devices the self loadingdue to gate terminal comes into picture and it is observed that decreasingthe transistor size improves energy-delay product.The optimum operatingpoint is when the transistor self loading is same as the loading due to nextstage.In complex circuits this same method of optimizing will hold good.The transistors in the critical path should be sized accordingly.But as in[25], using minimum-sized devices can lead to low power design but it doesnot lead to an energy efficient design.
1.2.2. Technology Scaling
Another way to improve the energy-delay product is to improve the tech-nology.A mentioned in [21] & [26]in ideal scaling, all voltages and lineardimensions are reduced by a scaling factor of γ(<1). As the electric fieldin the devices and wires remains the same, the device current and wire ca-pacitances also scale as γ.Since the voltages also scale by γ,the switchingenergy per transition (CV 2)term scales as γ3. The delay of each logic gateimproves by gamma (td ≈ CV
i) . The energy-delay product decreases by γ4.
This means that if a scaling of 0.7 is introduced, then a chip can give thesame performance at (0.7)4 ≈ 0.25 of the previous power consumption. But
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in ideal scaling , the threshold voltage Vthdoes not scale in tune with thesupply voltage.Static power dissipation caused by leakage current throughthe OFF transistors will limit how low the threshold voltage can be scaled.Even with constant voltage scaling, the reduced capacitance improves boththe energy and delay, so their product scales as γ2.
1.3. Active power Reduction
There are two methods of reducing active power or dynamic power. Theyare
1.3.1. Activity Reduction
Energy consumption is proportional to the frequency at which signalschange state from 0 to 1 or vice-versa and to the capacitance on the signalline. This is true for every signal path in a system, whether it is a clocksignal, a data pin, or an address line. This implies that power consumptioncan be reduced by carefully minimizing the number of transitions. So acorrect choice of the number representation can have a significant impact onthe switching activity. For example, program counters in processors generallyuse a binary code. On average, two bits are changed for each state transition.Using a Gray code in which only single bit changes occur from one count toanother, can give significant energy savings.Many such coding techniqueshave been reported in literature that yield different power savings.[4, 25]
To reduce activity in synchronous logic, clock gating[28] is employed.Clock signal to a logic block is gated by a control signal, disabling clockwhen the particular logic block is not in use, thereby reducing the clocksignal activity and thus the overall active power consumption. Since clockaccounts for substantial activity in the logic, it results in considerable powersavings.This technique can be applied to signal other than clock that havelarge effect on the active power.
1.3.2. Supply voltage reduction
Since power consumption reduces quadratically with supply voltage, sup-ply voltage reduction can result in substantial power savings. There aretwo ways to employ supply voltage reduction without compromising perfor-mance—static and dynamic.
In dynamic supply voltage scaling[3], the chip is designed to deliver max-imum performance at highest supply voltage.When the performance demand
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is low, the chip is operated at lower voltage, delivering lower performance butwith substantial (quadratic) power reduction.The logic chip may also detectthe performance demand and adjust frequency and supply voltage accord-ingly [6]. A mobile microprocessor for example may detect peaks in perfor-mance requirement and accordingly adjust supply voltage and frequency todeliver the necessary throughput, thereby saving power and energy.
In static supply voltage reduction, multiple supply voltages are used.Figure 1.3 shows such a scheme using two supply voltages. Higher supply
voltage is used for performance critical blocks which run at higher speed andconsume higher power and lower supply voltages are used for blocks thathave less performance demand.There are several issues with multiple supplyvoltages that need careful evaluation. When a logic signal that emerges froma slow block is connected to the fast block, the signal levels are closer to thethreshold voltages of the transistors, and could consume excessive leakagepower and reduce noise margin. This scheme also requires additional powersupply grid, and associated support such as decoupling capacitors, to ensureerror free operation.
1.4. Leakage reduction
Even when a CMOS circuit is idle there will be a leakage componentof current that will always be present.This contributes significantly to thepower dissipation of the circuit.Leakage power is becoming a major part ofthe total power dissipation with newer technologies.Some of the methods ofreducing leakage power are discussed here.
1.4.1. Leakage reduction using dual Vt technology
Dual Vt design technique[2] can be used to reduce the subthreshold leakagepower.In this , the process technology provides two types of transistors viz.
high supply voltage
low supply voltage
slow slowfast
high supply voltage
low supply voltage
Figure 1.3. static voltage scaling using multiple supplies
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High threshold voltage (High Vt) and low threshold voltage ( Low Vt). Thehigh Vt transistors give slower logic with lower leakage whereas the LowVttransistors yield faster logic, but higher ( about 10 times the slower ones )leakage.Thus a selective usage of low and high Vt transistors will yield higherperformance with lower leakage.
1.4.2. Stacking technique
This method is used to reduce the standby leakage power.It uses the factthat and “off” transistor stack has an order of magnitude lower subthresh-old leakage than the individual transistors.To exploit stack effect in standbymode, the logic block needs to be placed in a state where all stacked transis-tors are turned off. This can be done manually, however, future design tooldevelopments may automate this process.A 1.5X to 2.5X reduction has beenreported using this technique[10] .
1.4.3. Supply gating
Supply gating or “sleep transistor” is another method used to reduce bothactive and standby leakage power[18].The concept is similar to clock gating,where power supply is “gated” using a high Vt transistor, to cut off the powerto a logic block .This method can reduce the leakage currents by 1000X;however there are several issues. First, the high Vt transistor in series withthe supply causes performance degradation.Second, the virtual supply railscould couple to noise, reducing noise immunity. Third, the virtual supplyrails require a careful local power grid design such that the logic state is notlost when the virtual supplies are collapsed.
1.4.4. System and architecture level power reduction
The above mentioned circuit design methods of power reduction try tominimize any one or more components of power dissipation as shown by equa-tion 1.2.There are power reduction methods adopted at system level wherealong with the above mentioned circuit design methods, system power dissi-pation is reduced by careful design of algorithms and data encoding[9].Thoughsoftware does not consume energy, the storage and execution of the softwareby the underlying hardware consumes energy.Execution of software involvespower dissipation for computation, storage and communication.The energyrequirement for storage is less compared to that required for execution. Thusmuch of power reduction using software deals with minimizing power in ex-ecution of the code.For example reading a data block from the memory re-
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quires signals to be sent from the CPU to the main memory.This signaling isreduced by using algorithms and employing cache memory structures whichtry to get the data as far as possible from the CPU registers or from the cache.Other methods include use of a simplified instruction set for simple decodingand execution, selective shut-down of unused blocks during the operation ofthe design etc.
1.5. Adiabatic or charge recovery based circuit design
Apart from the above mentioned circuit level techniques, one particularlyinteresting technique is the Adiabatic Circuit design technique[1].Here themain concern is the recycling of the charge that has been stored on thecapacitive nodes at the outputs.Usually in conventional CMOS circuits, theoutput capacitive nodes of any logic gate are either charged to power supplylevel or discharged to ground to get a logic ’1’ and logic ’0’.The discharging ofthese capacitive nodes when switching from logic ’1’ to logic ’0’ represents awastage of energy.Every time a capacitive node of capacitance C is dischargedto from voltage V to Ground, an energy equal to 1
2CV 2 is lost.Adiabatic cir-
cuits try to recycle this stored charge so that instead of discharging to ground,the stored charge is sent back to the power supply.Adiabatic logic circuits andthe related power supplies are designed accordingly so that charge recyclingis possible.Another important parameter that determines the efficiency ofthese circuits is the way the capacitance at the output charges.The chargingprocess and the charge recovery process are efficient only when the chargingvoltage is slowly varying one.
In the next chapter the basics of adiabatic circuits viz., The charging anddischarging process of a capacitor in RC circuit and the energy calculationsare discussed.Later a brief discussion on the already existing adiabatic logicstyles with their merits and demerits is given.
Chapter 2
Adiabatic Architectures
Adiabatic Circuits are based on recovering the energy stored in nodalcapacitances.For a given amount of energy stored in nodal capacitance, theenergy drawn from the source depends on the rate of drawing the chargefrom the source.Lower the rate of charging, less is the power drawn from thesource.In other words, the efficiency of charging depends on how slowly thecapacitance is charged.In adiabatic circuits, one would like to take advantageof this process and increase the efficiency by charging the capacitance slowlyin addition to pumping the stored energy back into the supply.
2.1. RC circuits and related Energetics
This section is a review of the charging and discharging processes occur-ring in RC circuits.The energy stored in a capacitor when it is charged to avoltage V in a series RC circuit is explained.
Consider a simple RC circuit as shown in the figure 2.1 .Assume thatinitially the charge on the capacitor is 0 and it starts charging at time t=0and that the voltage source is a step voltage source V u(t).At any instant oftime the voltage on the capacitor is v(t) .In order to charge the capacitor,the battery has to do work. The work done in transporting a small amountof charge dq to the capacitor requires an amount of work dW given by
dW = v(t)dq (2.1)
The total work done in charging the capacitor from 0 to Q coulombs is
W =
Q
0
v(t)dq (2.2)
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At any instant, the voltage across the capacitor is related to the chargeq(t) as v(t) = q(t)
C.Thus equation 2.2 becomes
W =
Q
0
q(t)
Cdq =
1
2CQ2 =
(CV )2
2C=
1
2CV 2 (2.3)
RC
V(t)
Figure 2.1. A simple series RC circuit
Note that the energy stored in the capacitor is the work done in chargingit and it is independent of the series resistance R.The energy supplied by thebattery is
Ebattery = Q.V = (CV ).V = CV 2 (2.4)
This implies that the energy dissipated by resistor is
ER = Ebattery −W =1
2CV 2 (2.5)
.Now consider the same capacitor charged using a ramp voltage instead of a
step voltage.Let the voltage source be Vs(t) = V tT.Where V is the peak voltage
reached by the supply over a period T .The differential equation describingthe charging of the capacitance is given by
Vs(t) = i(t).R +1
C
ˆi(t)dt
di(t)
dt+
1
RCi(t) =
V
T
Solving this linear differential equation with the initial condition i(0) = 0
gives i(t) = V CT
(1 − e−t/RC).Using this value for i(t), the Energy dissipatedacross the resistor during the entire duration of charging is
ER =
ˆ T
0
i2(t).Rdt
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ER =
T
0
(CV
T
)2
R(1− e−t/RC)2dt
Evaluating the above integral gives
ER =
(CV
T
)2
R
[T − RC
2(e−2TRC − 1) + 2RC(e
−TRC − 1)
]For T ≫ RC, the exponential terms can be neglected and the above
expression can be approximated to
ER =
(CV
T
)2
R
(T − RC
2(−1) + 2RC(−1)
)
ER =
(CV
T
)2
RT (1− 3RC
2T) u
CV 2
TRC
Thus the power dissipated across the resistor is approximately
ER =
(RC
T
)CV 2 (2.6)
Compare equation 2.6 with equation 2.5.The energy dissipated by theresistor can be reduced by choosing T ≫ RC.
Thus it is observed that a ramp charging waveform can charge a capacitoroptimally by dissipating lesser energy across the resistor.This is the reasonwhy most of the adiabatic circuits reported in literature use a Ramp type ora trapezoidal type of power clock waveform.
2.2. Previous Adiabatic Circuit techniques
Many adiabatic/charge recycling circuits for digital logic applicationshave been proposed in literature.An adiabatic circuit in strict sense mustfollow two rules viz.— Never turn on a transistor when there is a voltage potential between the
source and drain.— Never turn off a transistor when current is flowing through it.Theses 2 rules are observed generally to make sure that step variationsof current are not present and thereby unnecessary energy dissipation isavoided[8].Most of the adiabatic circuits in literature don’t follow these rulesstrictly.All the charge recycling type of circuits are generally referred to asadiabatic circuits.In this section we take a look at some of the prominent
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Q1 D1 C
out
in
phi
out
in
out out out
phi2phi1 /phi1 /phi2
phi1
phi2
Figure 2.2. ADL inverter
circuit techniques and analyze their various aspects like complexity, powerconsumption , draw-backs if any etc.
2.2.1. Adiabatic Dynamic Logic (ADL)
Adiabatic Dynamic logic was proposed by Dickinson & Denker[7] .AnAdiabatic Dynamic Logic inverter circuit is shown in figure 2.2.It consistsof a diode D1 with cut-in voltage Vγ and a transistor M with thresholdvoltage Vt. The capacitor represents the implied load due to subsequentstages.The power supply is a time varying clock φ. There are two basicstages of operation of this circuit, precharge and evaluate.In the prechargestate, the power-clock ramps up from 0 to Vdd, precharging the output nodethrough the forward biased diode D to a value of Vdd − Vγ.In the evaluatestage, the clock supply ramps down from Vdd to 0.Now if the input is logic ’1’,then M is ON, so the output is driven low and Vout = 0.If the input is logic ’0’,then the output remains at high level and Vout = Vdd − Vγ.So logic inversionis taking place at the output .For cascading this kind of gate, different clocksare required.If an inverter is driving a second inverter then the clock for thesecond inverter should be in phase quadrature as shown in figure 2.2.Thus afour phase clocking is required for proper cascadable operation.
2.2.2. Split Level Charge Recovery Logic (SCRL)
The Split Level Charge Recovery Logic (SCRL) was reported by Younisand Knight[30][?].
A good understanding of the working of this logic can be obtained byanalyzing a full cycle of the inverter gate circuit shown in figure [2.3]. It issimilar to a conventional CMOS inverter with the exception of added trans-mission gate at the output .The inverter is driven by two complimentarypower clocks φ and φ rather than Vdd and ground terminals.φ varies between
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input output
Ø/
ØP
P
x
Ø
Ø/
Vdd/2
Vdd
Vdd/2
0
0
Figure 2.3. SCRL inverter
Vdd and Vdd
2whereas φ varies between Vdd
2and 0 .The transmission gate at the
output is controlled by clocks P and P . Initially, the clocks φand φ are atVdd
2,the transmission gate is turned OFF by the clocks P and P and output
is also Vdd
2.After a valid input logic level is applied, the transmission gate at
the output is gradually turned ON by swinging P and P to Vdd and groundrespectively.Then the clocks φ and φ swing to Vddand ground respectively.Ifthe input to the gate is Vdd then the node marked x and the output willfollow φ to ground and if the input was at ground then the node x andoutput follow φ to Vdd. The fact that both φand φ start at Vdd
2and split
towards Vddand ground is the reason this family is called Split-Level ChargeRecovery Logic. After the output is sampled by a later gate, the transmissiongate is turned off and the clocks φand φ are gradually brought to Vdd
2and
the gate is ready to accept a new input.Although this leads to lesser powerconsumption compared to conventional CMOS, the circuit is very slow dueto the additional time lost in gradual switching of the nodes from Vdd
2to Vddor
ground and vice-versa.
2.2.3. 2N-2P logic
This circuit topology was proposed by Denker et. al[13] . The name comesfrom the number of transistors in a gate as each input requires 2 NMOS andthe overhead for each complete gate is 2 PMOS transistors. This circuituses differential input and output, so each input to a gate requires bothpolarities to be represented and each gate computes both a logic functionand its complement. The basic circuit for a inverter-buffer is shown in figure.Each NMOS input gets the corresponding positive and negative polarityinputs and the cross-coupled PMOS are connected to the power clock. Thetiming and logical operation of the gate is as follows .The circuit operationcan be divided into 4 phases based on the clock and input conditions. In
15
the reset phase the inputs are low, the outputs are complementary and thepower supply ramps down. The high output, because its PMOS is held inON state by the low output, will follow the clock down so that at the endof the reset phase both outputs will be low. In the wait (second) phase thepower-supply stays low, maintaining the outputs low (the necessary conditionfor the next logical gate, which is delayed by a quarter cycle, to perform itsreset phase) and the inputs are evaluated. Because the gate is “powereddown", the evaluation of the inputs will have no effect on the state of thegate. In the evaluate phase, the power supply ramps up and the outputs willevaluate to a complementary state. The half-gate with its input high willhave its output held low while the half-gate with its input low will followthe ramp up. At the end of evaluate phase, the outputs will always becomplementary. This condition is guaranteed by the inverse logic of the twohalf gates and their cross coupled PMOS’s (this is the reason that 2N-2Plogic must be differential). In the hold phase the power supply clock stayshigh while the inputs ramp down to low. Gate outputs remain valid forthe entire phase.Because there are four phases to the timing, there mustbe four quadrature clocks in a complete system, each clock 90 degrees inadvance of the previous clock. In this way, each logic phase in the systemholds its outputs valid while its successor is evaluating (ramping up) and itspredecessor is resetting (ramping down) and waits with its outputs both lowwhile its successor is resetting (down) and its successor is evaluating (up).
2.2.4. 2N2N-2D logic
This logic family was proposed by Denker et. al .This logic uses differ-ential signaling and hence each signal is represented by itself and its com-plement.A logic 0 is represented by a downward pulse on c and a logic 1is represented by a downward pulse on d.This design requires a four stageclock cycle as shown in figure [2.4].At the beginning of the cycle the clock ishigh at Vdd and the diodes ensure that the outputs are high. The evaluatephase begins when the clock ramps down to 0V from Vdd .During this phasethe inputs have to be valid.Assume that a=0 and b=1.Since a=0, no currentflows in that branch and the output c remains high.However, all transistors inthe right evaluation branch are on because b = c = 1 . Hence signal d followsthe clock down. The evaluation phase is followed by the hold phase whenthe output is valid logic signal and can be sampled by other logic gates.Theinput does not have to be valid at this time since both the clock and signaldare low at this time and turning the right evaluation branch on or off does
16
not affect the output.Similarly just because signal d is low, the left evaluationbranch is off, and the output d remains at logical 1 irrespective of the inputs.The last phase is the recharge phase when the clock ramps up to Vdd andbecause of the diodes, whichever output was low follows the clock to a logicalhigh.Cascading such logic gates requires the second gate to be operated froma different clock because the output is valid only during the hold phase whilethe inputs are required to be valid during the evaluation phase.
2.2.5. Quasi Static Energy Recovery Logic (QSERL)
QSERL proposed by K.Roy [29] [22]is based on conventional CMOS ap-proach with two additional diodes as shown in figure 2.5. One diode con-trols the PMOS tree charging path while the other controls the NMOS treedischarging path.Compared to the 2N2N-2D and 2N-2P, this logic circuitrequires only two complimentary sinusoidal clocks. QSERL gates are basedon the conventional CMOS logic gates. The diode on the top of PMOS blockcontrols the charging path.The diode on the top of PMOS block controls thecharging path,while the diode below the NMOS block controls the discharg-ing path.The power clock consists of two stages.The evaluation phase andthe hold phase.During evaluation phase the clock phi swings up and phi-barswings down.One of the two paths, the PMOS pull-up path or the NMOSpull down path ,is turned ON.Based on the present state of the gate we havefour cases which determine the output for next state.1. The output node X is LOW and the PMOS tree is turned ON.Then X
follows phi as it swings HIGH2. The output node X is LOW and the NMOS tree is ON.X remains LOW
and no transition occurs.3. The output node X is HIGH and PMOS tree is ON.X remains HIGH and
no transition occurs.
c
d
c
d
b
a
Figure 2.4. 2N2N-2D inverter/buffer
17
PMOSblock
NMOSblock
outin
phi
phibar
Figure 2.5. QSERL logic block
phi
in inb
out outb
Mp1 Mp2
Mn1 Mn2
Figure 2.6. ECRL inverter/buffer
4. The circuit node X is HIGH and the NMOS tree is ON. X follows phi-bardown to LOW.
2.2.6. Efficient Charge Recovery Logic (ECRL)
Efficient Charge Recovery Logic or ECRL was proposed by Yong Moon et.al[16][17] .A simple inverter circuit using ECRL is shown in the figure.Thisgate uses differential signaling i.e both input and its compliment are requiredfor proper functioning.If we assume ’in’ is HIGH and ’inb’ is LOW, at thebeginning of a cycle,when the clock phi rises, ’out’ remains at ground levelbecause ’in’ turn on MN2. ’outb’ follows phi1 though Mp1.When phi1 ishigh, the outputs hold valid logic levels.These values can be used in the nextstage. While phi1 falls down to a ground level, charge on outb’ returns itsenergy to phi1.This logic gate avoids usage of any diodes but still requires a4 phase clocking for proper pipelining( cascading ) of multiple stages.
18
2.2.7. Glitch-Free and Cascadable Adiabatic Logic (GFCAL)
This was proposed by N.S Reddy [20][19] and is based on a modificationof QSERL already discussed above. Instead of using two complimentaryclocks, φ1and φ1, a single clock is used.More specifically the logic makes useof a single triangular clock waveform .The load capacitance represents thecapacitance due to input of the next stage. The charging and discharging arecontrolled by two diodes D1and D2.The operation of this logic is explainedhere using an inverter shown in figure 2.7. Similar to QSERL, four casesarise based on the input and output conditions at the beginning of any cycle.1. Rising Vclk and input LOW.In this case the transistor M1 is ON , M2 is
OFF and the path M1-D1 allows the capacitor to charge to Vclk producinglogic HIGH at the output.
2. Falling Vclk and input LOW. In this case the capacitor remains chargeddue to the presence of diode which does not allow the discharge process.Thus a LOW input is still giving a HIGH at the output
3. Rising Vclk and input HIGH. Here the transistor M2 is ON and M1 isOFF and the path M2-D2 allows discharging of the capacitor only whenthe output is higher than Vclk(t) at any point. This discharge happensonly for a small duration and may not produce much change at output.
4. Falling Vclk and input HIGH. In this case, the output capacitor gets dis-charged in-case it was previously charged.Thus a logic LOW is obtainedfor a logic HIGH as input.
Vclk
out
in
M1 M2
D1 D2
C
Vclk
0
Vdd
Vout
Vin
Figure 2.7. GFCAL inverter
2.2.8. Overview
The above discussed logic approaches have their own advantages anddisadvantages.SCRL for example consumes lower power but requires many
19
devices for a logic gate.The SCRL inverter requires 4 transistors, a SCRLNAND requires 8 transistors.In genera ll more devices are required per logicfunction compared to conventional CMOS design approach.Another draw-back is the requirement of multiple clock phases required for larger circuits.
The 2N-2P and its modified versions like 2N2P-2D,2N2P-2N etc consumeless power but have requirements like differential inputs, multi-phase clockinputs.The ECRL logic requires four-phase clocking.Multi-phase clocking in-creases the design complexity of the clocking circuit and also increases thepower dissipation of the clocking circuit. Further the number of transis-tors per logic gate is more. For a M-input logic gate, the 2N2P-2N ap-proach requires 6M transistors, thus these gates are inefficient in terms ofchip area. Adiabatic Dynamic logic (ADL) gates have simple gates withminimum number of transistors among all adiabatic circuits. But still thegates require a four-phase clocking for cascading.The load capacitor in thesegates is charged irrespective of the input .The output logic levels are validonly during a particular phase of the clock cycle and this may produceunwanted outputs and limits the cascadability of this circuit.In additionto the above, there are several other architectures proposed for adiabaticoperation[15][14][23][5][27][24].However most of them are very complex andneed several clocks for their operation.The advantage one gets in reducingthe power dissipation is more than compensated by the use of several clocksand increase in number of transistors.However, GFCAL gates proposed byN.S reddy seem to be more simple with a single clock.The design is cascad-able and uses less number of devices than other adiabatic circuits other thanADL. For a logic gate of M inputs, it requires 2M transistors and 2 Diodes.Itmakes use of diodes to control the charging or discharging of the load ca-pacitor. This has a small drawback. The voltage drop ac cross the diodedue to cut-in voltage Vγ causes a power dissipation when current flows acrossit. The reported efficiency of 50% compared to conventional CMOS can befurther improved by an alternative technique which consumes relatively lessenergy.An attempt has been made to replace the diodes by switching MOSdevices and the outcome of this investigation forms the basis of this thesis.Inthe next chapter a modified GFCAL inverter is discussed.
Chapter 3
Modified GFCAL Logic
The GFCAL logic discussed in the previous section has its own draw-backs.The presence of diodes in the charging and discharging path resultsin a loss of energy when current flows across the diodes.Even.From a simplepoint of view , if a charge q flows through a forward biased diode having acut0in voltage of Vγ,then an energy of qVγis expended.If this diode path forcurrent flow is modified, significant energy reduction can be obtained.Basedon this idea, a modified form of the GFCAL circuit has been proposed. Fig-ure 3.1 shows the proposed modified GFCAL inverter.The transistors M1 andM3 form the charging path and M2,M4 form the discharging path.For anyapplied logic input, either the charging path or the discharging path will bevalid.Note that in a given stable logic state, only one branch will be valid.Thepower supply is a trapezoidal waveform varying between 0 and Vdd.Hereafterthis circuit will be referred to as MGFCAL circuit. In order to highlight themodification made in this circuit, the original GFCAL circuit is also shownin the figure 3.1.In the next section, the operation of the circuit is discussedwith step-by step discussion of various states the circuit might be in. Alongwith this ,the situation of the GFCAL circuit is also considered for the samestates.
3.1. Operation of the circuit
The working of this circuit can be understood by considering differentcases as follows
Case-1:Output capacitor initially uncharged & input is logic ’0’ Incase of the GFCAL inverter, the transistor M1 will be ON and the diodeD1 will conduct when the clock transitions from 0 to Vdd . This causes thecapacitor to charge and an output of logic ’1’ is obtained.
21
For the Modified GFCAL,first let’s consider that the load capacitor is inuncharged state and input is logic ‘0’.In this case, the transistor M1 turnsON and when the clock goes from 0 to Vdd,at some point where the powerclock voltage exceeds the threshold voltage Vthn of the transistor M3, it turnsON and starts charging the capacitor. So a logic ’0’ gives a logic ’1’ at theoutput.
Case-2:Output capacitor initially uncharged & input is logic ’1’ ForGFCAL circuit, this means, the transistor M2 is ON and M1 is OFF, andthe diode D2 allows discharging only when the clock transitions from Vdd
to 0.Thus a ’1’ at input gives ’0’ at output.For the modified GFCAL, thetransistor M2 will be ON but M4 will be OFF when the clock waveform istransitioning from 0 to Vdd.When the clock goes from Vdd to 0, M3 turnsOFF at some point and thus prevents discharging.So the capacitor remainsuncharged. Note that a small amount of charging may still take place initiallydue to the leakage currents .But still this is very small and doesn’t increasethe output level much.Thus a logic ’1’ at the input gives a logic ’0’ at theoutput.
Case-3:Output capacitor initially charged & input is logic ’0’ Thetransistor M1 will be ON and M2 will be OFF in GFCAL gate and onlycharging path is available through M1 and D1 when the clock transitionsfrom 0 to Vdd.Thus the capacitor can only charge and the cannot dischargethus keeping the output at logic ’1’.
In case of the modified GFCAL, when the output is ‘1’ or charged tosome initial voltage level, and input is ‘0’, the circuit remains in the samestate as before.This can be explained as follows.For input being logic ’0, thetransistor M3 is ON and allows charging through M3 when power clock goesfrom 0 to Vdd.So the output is logic ’1’.When power clock goes from Vddto 0,the transistor M3 is OFF and thus discharging is prevented. So a ‘0’ at theinput gives a ‘1’ at the output.
Case-4:Output capacitor initially charged & input is logic ’1’ ForGFCAL , this is same as case-2 with capacitor being initially charged.Thetransistor M2 will be ON and the charge through the capacitor dischargesthrough the diode D2 and M2 when the clock transitions from Vdd to 0.In themodified GFCAL circuit,M3 is ON and M3,M4 will allow the discharge ofthe capacitor while the power clock goes from Vdd to 0.M1 will be OFF andfurther charging will not take place when power clock goes from 0 to Vdd.Soa logic ’1’ at input gives a logic ’0’ at the output.
22
Vclk
M1 M2
M3 M4
CL
out
in
Vclk
out
in
M1 M2
D1 D2
C
Figure 3.1. Modified GFCAL (left) along with the original GFCAL inverter circuit
From the above discussion it is seen that in modified GFCAL the tran-sistors M2 and M4 which switch alternatively are seen to allow only eithercharging or discharging at a given time.Further these switching transistors arecontrolled by the power clock signal which controls this charging/dischargingprocess.So it is evident that the modified circuit can work satisfactorily asan inverter.In order to evaluate the performance of this modified inverter,simulations of the circuit on Hspice has been carried out which is describedbelow.
3.2. Simulation of the basic transistor based adiabatic
inverter
The circuit shown in figure 3.1 is designed using MOS models of TSMC180nm CMOS technology .The device length and width are taken as L =
0.18µm and W = 4µm for both PMOS and NMOS transistors.A load ca-pacitance of 200femtoFarads is chosen.The power clock is a trapezoidalwaveform varying between 0 and 3.3V.The rise time and fall time have bothbeen chosen as 20nanoSeconds. A time period of 100 nanoSeconds has beenchosen for the power clock as depicted in figure 3.2.The input waveform ischosen as a series of alternate 1s and 0s with a rise time of 1picoSecond anda pulse width of 1 µsec.
The output waveform shown in 3.3 represents broadly the inverted inputwaveform.However there appears in the output waveform a ripple superim-posed on the actual waveform.This ripple is due to the coupling of the power
23
Graph1
t(s)
0.0 100n 200n 300n 400n 500n 600n
(V
)
-2.0
0.0
2.0
4.0(V) : t(s)
v(vdd)
Figure 3.2. Power Clock waveform
Output waveforms
t(s)
0.0 2u 4u 6u 8u 10u
(V
)
0.0
1.0
2.0
3.0
4.0
(V
)
0.0
1.0
2.0
3.0
4.0
(V) : t(s)
input
(V) : t(s)
output
Figure 3.3. Input and Output waveforms obtained from HSPICE simulation
clock waveform on the output waveform.This is due to the MOSFET ca-pacitance coupling the power clock waveform with the output waveform.Thereasons for this are discussed in the next section.In general it is possible tominimize this ripple by choosing a very large load capacitor but this willlead to a reduction in the speed of the circuit.This clearly shows that theproposed inverter circuit replacing diodes by switched transistors seems towork satisfactorily.Further one may note, there are no unwanted outputs likeglitches.However it is necessary to evaluate its performance from the pointof view of power consumption, effect of clock frequency, effect of load capac-itance and effect of load capacitance and effect of input frequency.All theseaspects have been investigated and have been described below.
24
3.3. Qualitative discussion on the output waveforms
The output waveform for the inverter circuit with a square wave inputis shown in figure 3.3The output waveforms for the inverter circuit showa ripple. This is due to the power clock frequency getting coupled to theoutput voltage due the gate-source capacitance and drain-source capacitanceof the bottom transistors.The amount of this ripple depends on the relativevalues of capacitance cgs & cds of the transistor and the load capacitance.If alarge width transistor is taken with the assumption that better charging maytake place, there may be increased device capacitance which can lead to aincreased ripple.The amount of ripple depends on the values of capacitance ofload and the gate capacitance of the switching NMOS transistor that controlscharging.A discussion of this is given in the next chapter.
As far as the voltage levels at the output are concerned, they are notthe same as in a regular CMOS gate (0, Vdd).The maximum value i.e logic’1’ is less than Vdd − Vtn and logic ’0’ is Vtp.The Vtn term is the thresholdvoltage of the bottom NMOS transistor.When the capacitor gets charged,ithas to charge through a series connected PMOS and NMOS transistors. AnNMOS transistor cannot pass a good ’1’.With a Vgs > Vtn the output forNMOS transistor with V at drain gives a value of V −Vtnat the source termi-nal.Thus the output voltage level is less than Vdd − Vtn for logic ’1’. Similarexplanation goes for the observed logic ’0’ of Vtp due to the bottom PMOStransistor.Further dependence of the output waveform on various factors likeDevice Width,Load Capacitance etc. is discussed in the next section.
3.4. Effect of variation of Device parameters
In this section a discussion is given of the effects of different parameters onthe output waveforms of the inverter circuit.The output waveform has beenobserved to depend on parameters like the threshold voltages Vthof NMOSand PMOS transistors, the width of the transistors, the load capacitanceetc.These trends are discussed below
3.4.1. Effect of Variation of transistor widths
Increasing the width of a transistors allows the circuit to charge or dis-charge the capacitive nodes faster.This is due to the fact that, a larger widthallows more current to pass through the transistors and thus lesser time isrequired to charge the capacitors to a required voltage level.Although thecharging and discharging processes are accelerated,there are other effects of
25
increasing the device width.One effect is that large device dimensions meansthat large capacitance of gate-source and drain-source junctions.As seen fromthe circuit diagram in figure 3.1, the power clock is connected to the gateof the controlling transistors and the time varying clock is imposed on theoutput waveform due to this coupling.
Graph4
(V
)
0.0
1.0
2.0
3.0
t(s)
1u 1.5u 2u
(V) : t(s)
v(7)
Figure 3.4. Output waveform ripple with different device Widths.The minimumripple in the figure is with width of 2µm and maximum ripple waveform is with a
device width of 32µm.
Graph0
Pow
er
dis
sipatio
n
1.1u
1.2u
1.3u
1.4u
1.5u
width of transistor
0.0 5u 10u 15u 20u
Power dissipation : width of transistor
avg_pwr
Figure 3.5. Power dissipation with device width
26
This creates ripples in the output waveform which become prominent asthe device junction capacitance approaches the value of load capacitance.Thisis verified by direct simulations on the circuit. Other parameters like powerdissipation are also affected by device widths.An increase in device widthincreases the power dissipation of the circuit due to increased current flowthrough the charging and discharging branches.This is shown in figure 3.5
3.4.2. Variation with Load capacitance
As the load capacitance takes time to charge or discharge based on itscapacitance value, a large capacitance will lead to slow charging and dis-charging and small capacitance values will give very fast charge dischargetimes.However, a disadvantage of using smaller capacitance is the increasedripple observed in the output waveform.
VappliedVin
Cload
output
Cgs
Cload
Vapplied
output
Figure 3.6. Capacitance model to explain the ripple effect
A circuit model to explain this effect is given in figure 3.6 which consistsof two capacitances connected in series where the top capacitance representsthe coupling capacitance due to both controlling transistors and the bottomcapacitance is the load capacitance.
27
Figure 3.7. Variation in observed ripple for Logic ’1’ output for different capaci-tances
It is seen that at any point of time the applied voltage Vapplied is dis-tributed among the two capacitors in an inverse ratio of their capacitance.Asmaller coupling capacitance(device capacitance) gives a very small rippleand a large coupling capacitance gives a large ripple.
Figure 3.8. Variation in observed ripple for logic ’0’ output for different capaci-tances
So a trade-off is made in selecting the device width and load capacitance.Ahigher capacitance will give a smoother waveform but with reduced speed ofoperation..Thus an optimum value of capacitance is chosen in such a waythat it is higher than the cgs of the switching transistors and the rippleis kept at minimum with optimal operating speed.For the TSMC 180µm
technology, the coupling capacitance due to devices is found to be about
28
Figure 3.9. Power dissipation for various capacitance..
9.59fF.If the load capacitance is chosen as 200fF , then amount of ripplewill be 9.59fF
200fF× Vdd = 0.15V .
As far as power dissipation is concerned, the power dissipation is expectedto be constant with respect to load capacitance.Since energy is being recy-cled from the load capacitance, the load capacitance should not have mucheffect on the power dissipation except for a small increase in the power withincreasing capacitance.This small increase is due to the dissipation across theswitches.
3.4.3. Varying the clock power Frequency
The power clock is primarily responsible for efficient charging of the loadcapacitance.Theoretically, the power dissipation across the resistive switch i.ethe transistor, depends on how fast the charging or discharging waveform isvarying.An increase in power clock waveform frequency tends to increase thepower dissipation.The voltage level up to which the load capacitance chargesalso depends on the power clock frequency.If an extremely slow power clockis used, the output capacitance charges till Vdd as the clock rise time and falltime are made larger.Figure shows simulated average power consumption fordifferent rise-time,fall-time values of power clock.It can be seen that for largertime periods or slower frequencies, the power dissipation decreases.Howeverthere is a limit on the time period of the power clock.It can be at most equalto the input data pulse width.Even for this case, the input data and powerclock have to be synchronized for proper logic operation.
29
Figure 3.10. Average Power dissipation for different power clock time periods mea-sured for 8µsec for 1µsec pulse width input data
Varying the power clock frequency (Time period) shows that as the fre-quency increases, there is a slight fall in the maximum voltage (Logic ’1’)reached by the capacitor.The minimum voltage (Logic ’0’ ) also increases withclock frequency.For clock frequencies very close to the input data frequency, the output may not be satisfactory.The transmission delay between inputand output will depend on the clock frequency .The delay characteristics andtheir dependence on the frequency of power clock is discussed later.
3.4.4. Varying the input data frequency
Input frequency determines how often the logic switches between 1 and0 and thus influences the power consumption of the gate.The variation ofpower consumed for various input data pulse widths is shown in figure 3.11.It is observed that lower input frequencies(higher time periods )give a lowpower input.The minimum time period of the input signal can be equal tothe time period of the power clock.This gives the lowest power consumptionbut the input signal and clock should have a 1800phase difference in orderto get proper logic inversion.Thus usually the input signal and clock signalare chosen such that time period of clock is about 10 to 15 times that of theinput signal pulse width.This has two advantages.First, the clock and dataneed not be synchronized and second the transmission delay between inputand input will not cause appreciable change in output pulse width.
The output voltage levels do not change with input data frequency.Theoutput levels are decided by the power clock voltage levels and thresholdvoltage of the switching transistors. Delay between input and output is
30
Graph0
(−)
0.0
500n
1u
1.5u
toni(−)
0.0 1u 2u 3u 4u 5u
(−) : toni(−)
avg_pwr
Figure 3.11. Variation of power consumption with different input signal pulsewidths
also not affected by changing input data frequency.Delay characteristics aredependent on the clock frequency used.This is discussed in next section.
3.4.5. Delay characteristics and input output relations
Transmission delay is defined as the time difference between the inputand output signals measured at the instant they are at their 50% levels.Inthe present adiabatic inverter circuit, this delay depends on the power clockfrequency and also on the instant of time at which the input is switchingwith respect to the power clock signal.From the circuit operation it is clearthat the output capacitive node can switch i.e charge or discharge only whenthe power clock is switching from high to low or vice-versa.Thus if the inputsignal switches at the instant when the power clock is not switching , thenthe output has to wait till the power clock signal switches.Varying the delaybetween the power clock switching instant and the input signal, it is observedthat the delay varies from a minimum of 0nanoSeconds to a maximum ofone period of the power clock signal i.e 20nanoseconds.This variation intransmission delay with respect to the offset between input signal and powerclock is shown in figure 3.12.
Note that for offsets of more than one clock period, the the input will bealigned to the next clock switching instant and the delay again decreases toa minimum.This is because if the switching input and the power clock are
31
Figure 3.12. Delay characteristics with different offsets between input and powerclock
separated in time, then they can be at the maximum , one clock frequencyapart.Keeping in view this delay characteristics, it is suggested to keep thepower clock cycle period small with respect to the input signal.
3.5. Cascadability
The essential requirement for a digital logic gate to be cascadable is thatthe input voltage levels and the output voltage levels be same.But in spite ofthis requirement not being met in this logic approach, the circuit is cascad-able.For one stage the outputs are degraded from 0,Vdd to Vtp,Vdd − Vtn .Butthis voltage level depends on the supply levels.If the inverter circuit is givenVtn and Vdd − Vtp as input for logic ’0’ and logic ’1, then it is observed thatoutput logic levels are also the same as input.The inverter circuit is tested forcascadability by connecting 100 such inverters in a pipeline.It is observed thateven at the 100th stage output, the same voltage levels are maintained.Figure
32
3.13 shows some waveforms taken from some random stages of the 100 stagepipeline.
Graph0
(V
)
0.0
1.0
2.0
3.0
t(s)
500n 1u 1.5u 2u 2.5u 3u 3.5u 4u 4.5u 5u 5.5u 6u 6.5u
(V
)
0.0
1.0
2.0
3.0
(V
)
0.0
1.0
2.0
3.0
(V) : t(s)
v(n_10)
(V) : t(s)
v(n_11)
(V) : t(s)
v(n_92)
Figure 3.13. Some output waveforms taken from random stages
In this chapter, the modified GFCAL circuit has been introduced andits elementary characteristics like voltage levels, power consumption and de-lay characteristics have been discussed.In the next chapter an approximateanalysis of the inverter circuit is taken considering the MOSFETS as idealswitches and having a ON resistance of R in the charging and dischargingpath.
Chapter 4
Mathematical model of the adiabaticinverter circuit
The charging and discharging pattern of the adiabatic inverter and thevariation of the waveform with different parameters is further investigated byconsidering the charging and discharging branches as composed of resistorswhen the corresponding branch is active. Assuming that the combinationof PMOS and NMOS in series acts as a resistor of value R when both thetransistors are ON, it can be seen that both the charging and dischargingbranch present the same resistance path.Although the transistors are notcompletely ON for the whole charging or discharging process, we assume thisto simplify our analysis.
4.1. Charging process
During charging, when the input is logical ’0’, the MOSFET M1 is ONand as Vclk increases from 0 to Vdd, the capacitor is charged through thetransistor M3. The clock voltage reaches its peak value Vdd in a time T.Theequation for clock waveform can be written as
Vclk(t) =Vddt
T
The clock reaches a value Vththe threshold voltage of the MOSFET M3at time Tth.The voltage Vcacross the load capacitor C after Tthis given by
Vddt
T= RC.
dVcdt
+ Vc
dVcdt
+1
RC.Vc =
1
RC(Vddt
T)
This is a linear differential equation of the form dydx
+ P (x)y = Q(x) forwhich the complete solution is of the form ye
´P (x)dx =
´Q(x)e
´P (x)dxdx+K
The solution becomes
34
in
out
C
==
Vdd Vdd
R
C
T
T
0
Vdd
Vdd
0
Figure 4.1. simplified model of the charging path
Vc(t)et
RC =1
RC
VddT
ˆte
tRC dt+ V0 (4.1)
which gives
Vc(t) = e−tRC
(1
RC
VddTRC.e
tRC (t−RC) + V0
)So the complete solution after simplifying is
Vc(t) =VddT
(t−RC) + V0e−tRC
The equation for current is obtained by differentiating 4.1 as ic(t) = C dVc
dt
which gives
ic(t) = CVddT− V0
Re−tRC
4.1.1. Energy during charging
The energy consumed by the circuit during charging process is evaluatedas
Echarging =
ˆVclk(t)
(Vclk(t)− Vc
R
)dt
which is equal to
1
R
ˆV 2clk(t)−
1
R
ˆVclk(t)Vcdt
In the above expression, the first term becomes
35
1
R
ˆ (VddT
)t2 =
V 2dd
RT
t3
3
The second term is
1
R
ˆ (Vddt
T
)(VddT
(t−RC) + V0e−tRC
)dt
=1
R
(ˆ (VddT
)2
t2dt−RC
ˆ (VddT
)2
tdt+
ˆ (VddV0te
−tRC
T
)dt
)
=1
R
(VddT
)2t3
3− C
V 2dd
T 2
t2
2− VddV0
TCe
−tRC (t+RC)
So the complete expression for Echarging is
Echarging =1
R
(VddT
)22t3
3− C
V 2dd
T 2
t2
2− VddV0
TCe
−tRC (t+RC) (4.2)
Equation 4.2 should be evaluated between the limits T1and T2 which arethe times between which the charging path is valid.i.e
Echarging =[
1R
(Vdd
T
)2 2t3
3− C
V 2dd
T 2t2
2− VddV0
TCe
−tRC (t+RC)
]T2
−[
1R
(Vdd
T
)2 2t3
3− C
V 2dd
T 2t2
2− VddV0
TCe
−tRC (t+RC)
]T1
4.2. Discharge Cycle
The equation of clock voltage during discharge is
Vclk(t) =−VddT
t+ Vdd
Vclk(t) = Vdd
(1− t
T
)where the coordinates have been shifted to the origin to simplify the
derivation.When the input is logical ’1’, the transistor M2 is ON and when the clock
voltage Vclk(t) is falling, the load capacitor discharges through M4 and M2.The differential equation in this case is
dVcdt
+1
RCVc =
1
RCVdd
(1− t
T
)36
This again is a linear differential equation as in the case of charging.Thevoltage across the capacitor then is
Vc(t)et
RC =
ˆ1
RCVdd
(1− t
T
)e
tRC + V1
=VddRC
ˆ (1− t
T
)e
tRC + V1
=VddRC
(e
tRC
1RC
− RC
Te
tRC (t−RC)
)+ V1
Vc(t) = e−tRC
VddRC
(e
tRC
1RC
− RC
Te
tRC (t−RC)
)+ V1
Vc(t) = Vdd −VddT
(t−RC) + V1e−tRC (4.3)
The equation of current through across capacitor can be obtained as C dVc
dt
which gives
ic(t) = C
(−VddT
− V1
RCe−tRC
)
4.2.1. Energy consumed during the discharge cycle
The equation for Energy during discharge is
Edischarge =
ˆVclk(t)
(Vclk(t)− Vc
R
)dt
=1
R
ˆ (V 2clk(t)− Vclk(t)Vc
)dt
1
R
ˆV 2dd
(1− t
T
)2
dt− 1
R
ˆVclk(t)Vcdt
In the above expression, the first part is
=1
R
ˆV 2dd
(1− t
T
)2
dt =−V 2
ddT
3R
(1− t
T
)3
The second part is
1
R
ˆVclk(t).Vc(t)dt
1
R
ˆVddt
T
(Vdd −
VddT
(t−RC) + V−tRC
1
)dt
37
V 2dd
RT
t2
2− 1
R
V 2dd
T 2
(t3
3−RC
t2
2
)− 1
R
VddTV1RCe
−tRC (t+RC)
So the complete expression is
Edischarge =−V 2
ddT
3R
(1− t
T
)3
+V 2dd
RT
t2
2− 1
R
V 2dd
T 2
(t3
3−RC
t2
2
)− 1
R
VddTV1RCe
−tRC (t+RC)
Edischarge =V2dd
R
(t2
2T− T
3
(1− t
T
)3
− 1
T 2
(t3
3−RC
t2
2
)+
V1
TVddRCe
−tRC (RC + t)
)(4.4)
Equation 4.4 should be evaluated between T3and T4which are the timesbetween which the discharge path is valid.So the actual power dissipation isevaluated as
Edischarge =
[V2dd
R
(t2
2T− T
3
(1− t
T
)3
− 1
T 2
(t3
3−RC
t2
2
)+
V1
TVddRCe
−tRC (RC + t)
)]T4
−[V2dd
R
(t2
2T− T
3
(1− t
T
)3 − 1T 2
(t3
3−RC t2
2
)+ V1
TVddRCe
−tRC (RC + t)
)]T3
Combining equation 4.2 and 4.4 one may obtain the energy dissipated asEcharing − Edischarging. Each of these quantities are to be evaluated for theirrespective periods of charging and discharging.The instant T1 at which thecharging takes place can be evaluated as
VddT1
T= Vth
soT1 =
VthT
Vdd
T is the rise-time of the power clock . T2can be calculated as
VddT2
T= (Vdd − Vth)
T2 =(Vdd − Vth)T
Vdd
Assuming that the capacitance value is small so that charging of thecapacitor closely follows the rise-time.In case the charging and dischargingtime constants are large compared to rise time, one has to find out the value
38
1 1.5 2 2.5 3 3.50
0.5
1
1.5
2
2.5x 10
4
Vdd (volts)
En
erg
y (p
J)
Plot of energy vs power supply of inverter
Figure 4.2. Variation in Energy per Cycle of charging and discharging with Vdd
of the output voltage at the peak of the power clock.Further the chargingcontinues during the flat portion of the power clock till the voltage on thecapacitor is Vdd−Vth.Similar procedure is to be adopted for finding the T3andT4.Using these values of T1,T2,T3 and T4, Echarging and Edischargingcan becalculated.The difference between these two gives the energy dissipation inone charge discharge cycle. The typical numerical calculations carried out tocheck the accuracy is discussed later.
4.3. Performance Variation with Circuit Parameters
Using the equations for voltages and energies obtained in the above sec-tion, it can be seen how the different measurements like voltage levels, energyetc vary with parameters like load capacitance,Rise-time and fall time ofpower clock signal and so on.
It can be observed from the equations of the charging and discharging en-ergies that the energy is directly related to V 2
ddterm.So an increasing supplylevel will increase the energy dissipation.The dependence of energy on othercomponents like path resistance, frequency of power clock etc. is not directlyevident from the expressions.In order to get a clearer view of the dependenceof energy on resistance, the equations 4.2 and 4.4 are evaluated and plottedfor varying path resistance.It is seen that with decreasing resistance, the en-ergy consumption increases.This is in agreement with figure 3.5 where largerdevice width i.e smaller resistance devices have high power dissipation thansmall width devices.
39
Resistance in Ohms
3
2.5
2
1.5
1
0.5
Ene
rgy
per
cycl
e in
pJ
50004000300020001000
Figure 4.3. Variation in Energy per cycle with resistance of charging path
A similar approach is followed to determine the dependence of energyconsumption on the frequency of power clock.The power clock is a trapezoidalwaveform with equal rise time, fall time and ON time.Thus the expressionsfor energy are plotted by varying a single parameter T which represents boththe rise time and fall time and also represents the clock frequency. Figureshows that with increasing rise time i.e with slower frequencies the powerdissipation comes down.This is in agreement to the basic idea of adiabaticdesign i.e slower the charging lesser the power dissipation.Figure shows thedependence of energy on the load capacitance.Although, ideally there shouldnot be any change in energy consumption for different capacitances, a smallincrease is observed.Looking at the equations 4.2 and 4.4, one may realizethat there is a small component of extra energy dissipated due to the lastterm containing e
−tRC .Normally this value is so small that it may be ignored.
4.4. Efficiency estimation
In order to estimate the efficiency of the MGFCAL circuit, the abovemathematical model is used assuming the ON resistance of the MOS switchesto be R in the charging and discharging paths.The ON resistance is estimatedusing a setup where a capacitor of known value is charged through two seriesconnected NMOS and PMOS transistors. A step voltage is applied at one endto this combination and the output charging characteristic is considered.Fromthis exponential charging characteristics, the rise-time is estimated as
40
5000
4000
3000
2000
1000
0
Ene
rgy
per
cycl
e in
fJ
Risetime , Fall time of clock T
80706050403010 20
Figure 4.4. Energy per cycle with varying T (Rise Time, fall Time)
Tr = 2.2R.C
where the values of C and Tr are known from simulations and R is cal-culated.Such calculation although may not be accurate but gives a simplemethod of approximating the non-linear resistance characteristics of the MOStransistor.For series connection of NMOS and PMOS transistors of 180µm
technology with dimensions of L = 180nm and W = 4µm, the resistanceapproximated using this method is approximately 5KΩ.The power clock hasa maximum value of 3.3Volts and C = 200fF.Using these values in the ex-pressions for energy obtained in the previous sections,the energy values areobtained as
Echarging = 26.2× 10−12J
Edischarging = 15× 10−12J
From these values, the percentage of energy lost is calculated as
%Lost =Echarging − Edischarging
Echarging× 100 =
26.2− 15
26.2× 100 ≈ 42%
41
capacitance 200fF to 2pF
0.0
0 0.0 0.0 0.0 0.0
Ene
rgy
in p
J (
Yra
nge
-50p
J to
50p
J)
0
0.0
Figure 4.5. Variation in Energy per cycle of charging discharging for different ca-pacitive loads
In other words an efficiency of 58% is obtained.It may be seen from this description given here that the estimated en-
ergy recovered is about 58%.In conventional CMOS circuits the entire energydrawn is dissipated.Thus this circuit may be considered as 58% more effi-cient.From the result reported in [20] , the GFCAL circuit consumes about50% of energy that CMOS consumes.Thus the present modified GFCAL con-sumes 8% less energy than GFCAL circuit and 58% less energy than CMOScircuit.
Chapter 5
Logic design based on MGFCAL
The inverter design is used as basis for the design of other logic blockssuch as NAND and NOR gates.Any logic gate can be designed in theoryusing this approach of two paths,one for charging and other for discharg-ing.The paths should have the appropriate,pull-up and pull-down circuitryto provide required logic operation.In this chapter ,the NAND and NOR gatesare discussed and some of the circuit properties are studied.Finally in orderto characterize the power consumption of the gates, the gates are subject topseudo-random input bit streams and the average power consumed is mea-sured for comparison with conventional CMOS gates.As a further extensiona combinational block of 8-bit ripple carry adder has been designed.It is alsoshown that , implementation of sequential blocks is also possible.
5.1. NAND function
The NAND function can be obtained by using the circuit shown in figure5.1.The operation of this gate is similar to that of the inverter i.e the chargingand discharging of the output transistor is controlled by the pull-up andpull-down paths and the controlling transistors.In order to realize a NANDoperation, consider the truth table for NAND gate.It is required that theoutput should be logic ’0’ when both inputs are logic ’1’. For this case wecan have a series connection of two NMOS transistors in the discharge path.For the logic ’1’ output, the inputs can be any of the three combinations i.e01, 10, 00.These three cases can be taken care by using a parallel combinationof two PMOS transistors in the charging path.The controlling transistors atthe bottom remain as it is in all logic gates.It can be seen that output cancharge from rising Vclk if the pull-up path comprising of M1,M2 and M5 isconducting.This occurs for inputs of A=0 , B=0 or A=B=0.So the outputfor this is 1.The output capacitor discharges to Vclk if A=B=1 and Vclk is
43
Vclk
A
B
A B
out
Cload
M1
M2 M3
M4
M5 M6
Figure 5.1. NAND gate
falling from Vdd to 0.Thus a NAND operation is realized.A NOR gate can berealized in a similar manner.
5.2. NOR gate
The NOR function is obtained by using the circuit shown in figure 5.2 .Theoperation of this gate is similar to that of the NAND gate above.The outputcan charge from rising Vclk if the pull-up path comprising of M1,M2 andM5 is conducting.This occurs for inputs A=B=0.So the output for this willbe 1.The output capacitor will discharge to Vclk if A=1 or B=1 or A=B=1and Vclk is falling from Vdd to 0.Thus a NOR operation is realized.It canbe observed from the circuit diagrams of both NAND and NOR gates thattheir pull-up and pull-down paths resemble the conventional CMOS gatestructures.Thus any logic function can be realized by having the appropriatepull-up and pull down paths in the basic inverter configuration.
5.3. Simulation results
The NAND and NOR gates circuits are simulated using HSPICE.Figure5.3 shows the input and output waveforms for NAND gate.It is observedthat the output shows levels similar to the inverter circuit.An explanationof the observed voltage levels was already given in section 3.3.The outputlevels are lesser than Vdd and 0 due the presence of the switching transistorsM5 and M6 . The pull-up path comprising of M1,M2 and M5 has to pass a
44
Vclk
A BA
B
out
Cload
M1
M2
M3 M4
M5 M6
Figure 5.2. NOR gate
Adiabatic NAND
(V
)
0.0
1.0
2.0
3.0
t(s)
0.0 2u 4u 6u 8u 10u
(V
)
0.0
2.0
4.0
(V
)
0.0
2.0
4.0
(V) : t(s)
v(out)
(V) : t(s)
v(a)
(V) : t(s)
v(b)
Figure 5.3. NAND gate simulation waveforms
good logic ’1’ but allows a voltage less than Vdd − Vth due to the presence ofM5.Similarly the pull-down path comprising of M3,M4 and M6 passes Vth as alogic ’0’.The amount of ripple in the output waveform shows a dependence onthe load capacitor as discussed earlier.A larger capacitance will lead to slowercircuit but smoother outputs and a smaller capacitance gives faster circuitwith a considerable ripple due to clock waveform.In any case , for optimumperformance, the load capacitor should be chosen to be considerably largerthan the gate capacitance of the switching transistors as the amount of rippledepends on the ration of Cload and Cgs as explained earlier.
Since logic circuits with two inputs have been considered,the power con-sumed in a given time depends on the input bit pattern and how many times
45
Window No. Power Consumed ( µWatts)1 0.29132 0.31423 0.30914 0.35015 0.29606 0.31167 0.35308 0.33429 0.326210 0.333311 0.323112 0.303713 0.348214 0.339115 0.3515
Table 5.1. Average Power measurements for adiabatic NAND gate at various50µsec duration windows.
the load capacitor charges or discharges.Therefore, in order to better estimatethe power consumption of the circuits, they are fed with two pseudo-randombit sequences of large length and the average power consumed is measuredduring different time slots of equal duration.
5.3.1. Estimating the power consumption by simulation
A pseudo-random sequence is a bit sequence that appears to be randomfor small duration of observation but is periodic after a certain length.Pseudo-randombinary sequence are usually generated using a Linear Feedback Shift Register(LFSR).(Refer Appendix B)
Two bit sequences obtained from same LFSR with different seed values aregiven as input to the NAND and NOR gates.Two seed values ’1’ and ’2’ havebeen used to obtain different sequences which are applied to the inputs A andB of the gate.Here for a bit width of 1µSec ,time windows of 50µSec durationhas been chosen and the average power consumed in this windows at varioustimes is measured and a average is calculated from these values.This averagemeasurement gives a better estimate of the average power consumption ofthe gates. Tables 5.1 and 5.2 show these measurement results. A similarmeasurement is made on conventional CMOS gates for comparison purpose.Tables 5.3 and 5.4 show the measurements for corresponding ConventionalCMOS gates.It is observed that the efficiency of the MGFCAL depends onthe input data used.In general NOR based circuits for MGFCAL have less
46
Window Power Consumed ( µWatts)1 0.21112 0.26583 0.30784 0.27955 0.26686 0.30237 0.26518 0.31039 0.288810 0.310211 0.302812 0.287013 0.300114 0.2707
Table 5.2. Average Power measurements for adiabatic NOR gate at various 50µsecduration windows.
Window No. Average Power(µW )1 0.61882 0.69493 0.69894 0.78515 0.64416 0.69987 0.68798 0.75829 0.729610 0.755912 0.729313 0.674214 0.786815 0.7588
Table 5.3. Average Power measurements for Conventional CMOS NAND gate atvarious 50µsec duration windows.
47
Window Average Power (µW )1 0.52552 0.50333 0.33694 0.30555 0.42146 0.36387 0.47568 0.31129 0.416910 0.308112 0.359713 0.479014 0.362615 0.4472
Table 5.4. Average Power measurements for Conventional CMOS NOR gate atvarious 50µsec duration windows.
efficiency and this can be attributed to the number of times switching takesplace.the average efficiency of MGFCAL NAND with respect to conventionalCMOS is 57.67%. For NOR , the efficiency is less at 44.78%.This dependson the number of times charging or discharging of the capacitor is occurringat the output.
Using the above discussed gates any combinational logic can be imple-mented.As an example to this, an 8-bit ripple carry adder is designed asdiscussed next.
5.4. Further application-an 8-bit adder circuit.
The NAND and NOR gates being universal gates are sufficient to designany combinational logic circuit.To test the effectiveness of these gates a sim-ple 8-bit Ripple carry adder is designed.The other gates used for this adderlike Ex-OR have been derived using combination of NAND gates discussedabove. Using such Ex-Or gates a full adder is realized.Figure 5.4shows theimplementation of Ex-OR gate and figure shows typical waveforms for a fulladder using this Ex-OR gate.
48
A B
A B
Figure 5.4. XOR gate realized using NAND gates
Figure 5.5. Typical waveforms for a full-adder module
A 8-bit ripple carry adder was designed and the performance of this addercircuit is tested by applying known bit pattern to the two inputs.A schematicfor the 8-bit ripple adder is shown in figure 5.6. A 11001100 and 10101010pattern was applied and the circuit has been observed to work satisfacto-rily.Power measurement on the MGFCAL adder circuit and conventionalCMOS adder circuit for this combination are shown in Table 5.5 .
49
sum
carry
A
B
==
A
B
CC
sum
carry
FA
A0A1A2A3A4A5A6A7 B0C_inB1B2B3B4B7 B5B6
S0S1S2S3S4S5S6S7C_out
FA0FA1FA2FA3FA4FA5FA6FA7
Figure 5.6. A 8-bit ripple carry adder derived using the available NAND gates
Architecture Power measuredConventional CMOS 8-bit adder 4.75mW
MGFCAL based 8-bit adder circuit 1.85mW
Table 5.5. Power measurements for ripple carry adder
Along with a combinational logic sequential logic is also possible but thestrict requirements on clocks and delays may not be achievable due to deviceconstraints and power constraints.A JK latch implementation is discussedfor this purpose.
5.5. Implementation of sequential blocks using Modified
GFCAL gates
In the previous sections, combinational blocks using MGFCAL were pre-sented. Any logic design style will be useful if it is possible to implementboth combinational as well as sequential blocks with it. In order to show thatthe present adiabatic style viz. MGFCAL can be used to design sequentialblocks, a latch implementation is shown.
5.5.1. A JK Latch
Conventionally a latch is a clocked gateway for data. The data at theoutput of the latch changes according to the input only when the clock is
50
J
K
Clk
Q
Qb
Figure 5.7. JK Latch
Circuit Average power (µW )JK latch conventional CMOS 5.643MGFCAL based JK latch 1.979
Table 5.6. Power measurements for JK Latch
enabled. When the clock is disabled, the data at the output remains ’latched’to the previous value it had when clock was valid.Figure 5.7 shows a JKlatch.It makes use of NAND gates. When the clock signal clk is logic ’1’,theoutputs Q and Q will change as the inputs J and K change.When clock islogic ’0’ , the outputs Q and Q remain latched to the previous values. Thissame circuit can be used as the basis for design of a MGFCAL based JKflip-flop. The NAND gate discussed in the previous section can be used inplace of the conventional NAND gate and required latch functionality can beobtained.Power measurement for this latch in comparison to a conventionalCMOS version are given in table 5.6
Typical waveforms for the JK latch are shown in the figure.The powermeasurements show that MGFCAL based latch consumes about 64% lesspower than the conventional circuit.
Thus the MGFCAL logic can be used to implement combinational blocksas well as sequential blocks.
It has been shown that the MGFCAL based logic design style is efficientand power saving is up to the tune of 60% for various simple logic blocks.Thisis a significant improvement over the GFCAL circuits which gave power sav-ings of 50% compared to conventional CMOS circuits.The replacement ofdiode from the original GFCAL logic circuits with switching transistors thatemulate a diode action and don’t form a diode like potential barrier forcurrent flow has indeed lowered the power consumption.In addition to powersavings, the architecture follows the simplistic design process of GFCAL withminimal number of components compared to other adiabatic logic styles likethe 2N2P-2D,2N-2P2N etc.
Figure 5.8. Typical waveforms for the JK latch
52
Chapter 6
Conclusion
This thesis deals with a method of cutting down the wastage of energyin conventional CMOS circuits.In CMOS circuits the energy stored in thenodal capacitance is wasted by discharging that energy to ground dependingon the signal that is present .This thesis reports ways of pumping the energystored in the capacitor back to the power supply thus reducing the energydissipated or energy wasted.Such circuits are referred to as adiabatic circuits.
There have been several approaches reported for recycling the energy andit has been shown that GFCAL[20] approach generally results in a saving of50% of what is normally dissipated in similar CMOS circuits.GFCAL cir-cuits make use of diodes to limit the direction of current in the circuits.Itis not only difficult to realize diodes in CMOS technology but they alsocontribute to considerable power dissipation.This thesis reports a methodreplacing these diodes by MOSFETS which can be easily fabricated withCMOS technology.This approach not only simplifies the technology neededto realize these adiabatic circuit but increases the power saving to about60% compared to CMOS circuits.It has been clearly demonstrated by carry-ing out the performance characteristics like the logic level variations,effect ofthe characteristics of input signal, power clock signal etc., that these circuitscan be used in large cascadable circuits and systems without any loss ofperformance.Simple circuits like logic gates and block level implementationslike adder have been realized.The adiabatic circuits that have been investi-gated are with a technology of 0.18µm with BSIM3V3 model parameters.Thepresent day technologies are with much smaller feature sizes and the devicemodels also are much more complicated.It is quite likely that further modi-fications in the circuit topology may be needed if one wants to optimize theperformance with advanced technologies.
It may further be noted that these circuits are to be fabricated and effectof parasitics on the performance is to be finally evaluated before they find
53
their way in real life electronic gadgets.It is believed that future low powerelectronic systems should not use not only lower currents and lower voltagesbut the wastage of energy must be reduced through the use of adiabaticapproach.
Appendix A
The MOS transistor and CMOS basedcircuits
This section is a brief introduction to the Metal Oxide SemiconductorField Effect Transistor (MOSFET) which is the most common type of tran-sistor in use in modern Integrated Circuit (IC) Design.The basic structureof a MOSFET is shown in the figure.It consists of a doped semiconductorsubstrate in which two regions of opposite doping are diffused.These regionsare called Source and Drain.An insulating layer (usually SiO2) separates themetal or poly silicon gate terminal from the semiconductor.Thus the nameMetal Oxide Semiconductor.Based on the kind of substrate and the kind ofimplants for source and drain and the kind of carriers responsible for currentflow between source and drain terminals, there are two kinds of transis-tors in MOS technology.They are n-channel NMOS(having p-type substrateand n-type source and drain regions) and p-channel transistor PMOS(havingn-type substrate and p-type source and drain regions).A simplified view of an-channel MOS transistor is shown in figure A.1.A positive voltage appliedto the Gate terminal first causes a depletion if mobile charge carriers inthe substrate under the oxide layer.A further increase in the applied gatevoltage leads to a formation of region with excess electrons thus makingit n-type.Since the substrate is p-type for n-channel transistor, the n-typelayer formed below the oxide layer is referred to as an inversion layer.Thegate-to-source voltage at which the inversion layer becomes as much n-type,as the substrate is p-type is commonly called the threshold voltage.Whenthe gate to source voltage vgs is more than vth the device conducts currentfrom source to drain on applying a voltage and when it is less than vth
the device conducts practically no current.This property of controlling theconducting path with the help of applied gate voltage is used in realizingdifferent circuits in both analog and digital domain.The dependence of thedrain to source current on the drain to source voltage for different values ofgate voltages is shown in the figure A.2.
The current voltage relationship is mostly non-linear.There is a small
55
G
D S
n+ n+
p-substrate
Figure A.1. n-channel MOS transistor
region in which linearity is observed and this region is called the triode regionof operation.This occurs for vds < vgs − vth.The equation of drain sourcecurrent in this region is given by
Id = k′W
L
((Vgs − Vth)Vds −
Vds2
)where k′is a parameter depending on the process technology and W and Lare the length and width of the conducting channel in the transistor.Beyondvds = vgs−vth, the drain current is essentially independent of vds.This regionis called saturation region.The current in this region is given by the equation
Id = k′W
2L(Vgs − Vth)
2
For vth < 0 the transistor is in cut-off mode and no current flows.In all abovecases, the proper operation of the device requires the source-substrate anddrain-substrate junctions to be reverse biased so that no current flows fromsource or drain to substrate.This condition is met by connecting the substrateto the most negative potential available in a design which is usually groundterminal.
The above discussion is equally applicable for a p-channel transistor orPMOS.In most of the circuits a combination of PMOS and NMOS transistorsis used and this design methodology is called CMOS (Complimentary MetalOxide Semiconductor) design. A simple example of such design is a Inverteror NOT gate as shown in figure A.3.
Usually the threshold voltage of NMOS devices is positive and that forPMOS devices is negative.If the two devices are connected as shown in thefigure, then an input voltage of 0 makes the PMOS ON and the output nodeis pulled up to Vdd. If a voltage of Vdd is applied at input then NMOS isON and output node is pulled down to 0.Thus a logic inversion is takingplace.Note that the pull-up and pull-down processes have to charge or dis-
56
Graph0
(A
)
0.0
1.0m
2.0m
VOLTS(V)
0.0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0
(A) : VOLTS(V)
-i(vd)
Figure A.2. NMOS current voltage characteristics
Vdd
outin
Graph0
(V
)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 20n 40n 60n
(V
)
-1.0
0.0
1.0
2.0
(V) : t(s)
v(in)
(V) : t(s)
v(out)
Figure A.3. CMOS Inverter with typical output waveforms
57
A B NAND out0 0 10 1 11 0 11 1 0
A B NOR out0 0 10 1 01 0 01 1 0
Table A.1. Truth tables for NAND and NOR gates
Vdd
A B
A
B
out
Vdd
out
A
A
B
B
Figure A.4. CMOS NAND and NOR gates
charge the output nodal capacitance.In general any logic gate can be realizedwith appropriate combination of PMOS and NMOS devices.A simple NANDimplementation is discussed here to demonstrate this. A NAND gate hasthe truth table as given in A.1 . Thus it is required that output be logic’0’ only when both inputs are logic ’1’. To get this functionality we wantthe output node capacitance to be pulled up for combinations of 00, 01 and10.The output should be pulled-down for the combination of 11. This canbe achieved by using the circuit shown in figure A.4.A NOR gate can also beobtained in a similar way.
Appendix B
Linear Feedback Shift register
In order to estimate the average power consumed by logic gates or circuitwith multiple inputs, random input bit sequences are required.One way toproduce such sequences is to use a Linear Feedback Shift Register.An LFSRis a shift register whose input is a linear function of two or more previousbit positions( also called taps). Ex-OR and Ex-NOR are the only linearcombinations of single bits possible.There are many possible configurationsand the length of the bit sequence produced depends on the position of thetaps.Only some combination of taps will generate a maximal sequence witha period of 2n − 1.A simple example of an LFSR with taps at 3rd and 4rdpositions is shown in figure B.1.
1 0 0 1
1
1 2 3 4
Figure B.1. A 4-bit LFSR
The value of the shift register before start of the sequence is called aseed.When using a Ex-OR based LFSR, a seed of all 0’s is invalid.Similarlya seed of all 1’s is invalid for a Ex-NOR based LFSR.
The arrangement of taps for feedback in an LFSR can be expressed as apolynomial mod 2. This means that the coefficients of the polynomial mustbe 1’s or 0’s. This is called the characteristic polynomial.For the LFSR offigure B.1, the characteristic polynomial is
x4 + x3 + 1 (B.1)
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The 1 at the end in the characteristic equation is the input bit to theLFSR at the beginning of the sequence.The length of this LFSR is 15 (i.e24−1)which means it goes through all the possible 15 states before returningto initial state.For the purpose of giving inputs to the NAND and NOR gates,an LFSR of length 1023 has been chosen.This requires a 10-bit shift registerwith taps at positions 7 and 10.The characteristic polynomial is
x10 + x7 + 1 (B.2)
Thus the output sequences obtained from such an LFSR can be used asa input to digital circuits to gauge their power dissipation characteristics.
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List of Figures
1.1. Energy,delay Vs. Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 51.2. Energy,Delay Vs. Transistor Width . . . . . . . . . . . . . . . . . . . 61.3. static voltage scaling using multiple supplies . . . . . . . . . . . . . . 8
2.1. A simple series RC circuit . . . . . . . . . . . . . . . . . . . . . . . . . 122.2. ADL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3. SCRL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.4. 2N2N-2D inverter/buffer . . . . . . . . . . . . . . . . . . . . . . . . . 172.5. QSERL logic block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.6. ECRL inverter/buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.7. GFCAL inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. Modified GFCAL (left) along with the original GFCAL inverter circuit 233.2. Power Clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.3. Input and Output waveforms obtained from HSPICE simulation . . . 243.4. Output waveform ripple with different device Widths.The minimum
ripple in the figure is with width of 2µm and maximum ripplewaveform is with a device width of 32µm. . . . . . . . . . . . . . . . . 26
3.5. Power dissipation with device width . . . . . . . . . . . . . . . . . . . 263.6. Capacitance model to explain the ripple effect . . . . . . . . . . . . . 273.7. Variation in observed ripple for Logic ’1’ output for different capacitances 283.8. Variation in observed ripple for logic ’0’ output for different capacitances 283.9. Power dissipation for various capacitance.. . . . . . . . . . . . . . . . . 293.10. Average Power dissipation for different power clock time periods
measured for 8µsec for 1µsec pulse width input data . . . . . . . . . 303.11. Variation of power consumption with different input signal pulse widths 313.12. Delay characteristics with different offsets between input and power
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.13. Some output waveforms taken from random stages . . . . . . . . . . . 33
4.1. simplified model of the charging path . . . . . . . . . . . . . . . . . . 354.2. Variation in Energy per Cycle of charging and discharging with Vdd . 394.3. Variation in Energy per cycle with resistance of charging path . . . . 40
64
4.4. Energy per cycle with varying T (Rise Time, fall Time) . . . . . . . . 414.5. Variation in Energy per cycle of charging discharging for different
capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1. NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.2. NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.3. NAND gate simulation waveforms . . . . . . . . . . . . . . . . . . . . 455.4. XOR gate realized using NAND gates . . . . . . . . . . . . . . . . . . 495.5. Typical waveforms for a full-adder module . . . . . . . . . . . . . . . . 495.6. A 8-bit ripple carry adder derived using the available NAND gates . . 505.7. JK Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515.8. Typical waveforms for the JK latch . . . . . . . . . . . . . . . . . . . 52
A.1. n-channel MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . 56A.2. NMOS current voltage characteristics . . . . . . . . . . . . . . . . . . 57A.3. CMOS Inverter with typical output waveforms . . . . . . . . . . . . . 57A.4. CMOS NAND and NOR gates . . . . . . . . . . . . . . . . . . . . . . 58
B.1. A 4-bit LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
List of Tables
5.1. Average Power measurements for adiabatic NAND gate at various50µsec duration windows. . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2. Average Power measurements for adiabatic NOR gate at various50µsec duration windows. . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3. Average Power measurements for Conventional CMOS NAND gate atvarious 50µsec duration windows. . . . . . . . . . . . . . . . . . . . . 47
5.4. Average Power measurements for Conventional CMOS NOR gate atvarious 50µsec duration windows. . . . . . . . . . . . . . . . . . . . . 48
5.5. Power measurements for ripple carry adder . . . . . . . . . . . . . . . 505.6. Power measurements for JK Latch . . . . . . . . . . . . . . . . . . . . 51
A.1. Truth tables for NAND and NOR gates . . . . . . . . . . . . . . . . . 58
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