Verilog-A Language By William Vides William Vides Edited by Dr. George Engel

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Transcript of Verilog-A Language By William Vides William Vides Edited by Dr. George Engel

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Verilog-A Language By William Vides William Vides Edited by Dr. George Engel Slide 2 Topics to be Covered b Background information b Analog System Description and Simulation b Types of Analog systems b Signals in Analog systems b Analog System simulation b Analog Model Properties b Analog Operators Slide 3 Background Information Background Information b Fundamental differences between digital and analog design. b Current level of abstractions achieved by Spice and Verilog HDL b Verilog -A as an extension of Spice Slide 4 Difference between Digital and Analog Design Always @ (enable) begin valid = 1b0; // do write cycle addr_lines = addr; data_lines = data; @ (negedge clk) begin valid = 1b1; end Top Down Refined from HDL Level Bottom-Up Transistor level Slide 5 Behavioral Gate Switch Circuit Higher level of abstraction Current Levels of Abstraction Achieved by Spice and Verilog Slide 6 Behavioral Gate Switch Circuit Higher level of abstraction Verilog-A as an extension of Spice Slide 7 Analog System Description and simulation b Structural Description a module is comprised of other child modulesa module is comprised of other child modules b Behavioral Description descriptions in a programmatic fashion with the Verilog-A languagedescriptions in a programmatic fashion with the Verilog-A language The module is defined in terms of the values for each signalThe module is defined in terms of the values for each signal b Mixed-level Descriptions Combine both Structural and Behavioral DescriptionsCombine both Structural and Behavioral Descriptions Slide 8 Modem Example modem modulator channel demodulator The modem system is made up of 1) the modulator 2) a channel 3) the demodulator Slide 9 Structural Description hierarchy Module: qam Instance: mod module: qam_mod Instance: c1 module: channel Instance: demod module: qam_demod Slide 10 Structural Description of the Modem System // Verilog A definition of the modem System `include std.va module modem( dout, din) inout dout, din; electrical dout, din; parameter real fc = 100.0e6; electrical clk, cin, cout; qam_mod #(.carrier_freq(fc)) mod (cin,din,clk); channel c1 ( cout, cin); qam_demod #(.carrier_freq(fc)) demod (dout,cout,clk); endmodule Slide 11 Structural Description Type of module instance Name of the instance created qam_mod # (.carrier_freq(fc)) mod ( cin, din, clk); Parameter name in child ( qam_mod) module assigned as: carrier_freq = fc Slide 12 16_QAM modem Example 2-bit d2a Serin_parout 2-bit d2a aq A sin( 2pi fct + pi/ 4) di dq ai A cos( 2 pi fct + pi/4) din mout A(t)cos( 2pifct + 0(t)) Slide 13 Verilog A mixed Signal definition of 16-QAM modulator `include std.va `include const.va module qam_mod( mout, din, clk); inout mout, din, clk; electrical mout, din, clk; parameter real fc = 100.0e6; electrical di1,di2, dq1, dq2; electrical ai, aq; serin_parout sipo( di1,di2,dq1,dq2,din,clk); d2a d2ai(ai, di1,di2,clk); d2a d2aq(aq, dq1,dq2,clk); real phase; Slide 14 Verilog A mixed Signal definition of 16-QAM modulator analog begin phase = 2.0 * `M_PI * fc* $realtime() + `M_PI_4; V(mout)