Introduction to Sequential Logic Circuits
38
Introduction to Sequential Logic Circuits (Class 8.2 – 3/7/2013) CSE 2441 – Introduction to Digital Logic Spring 2013 Instructor – Bill Carroll, Professor of CSE
Transcript of Introduction to Sequential Logic Circuits
Introduction to Sequential Logic Circuits (Class 8.2 – 3/7/2013)
CSE 2441 – Introduction to Digital Logic
Spring 2013
Instructor – Bill Carroll, Professor of CSE
Today’s Topics
• Sequential circuit models – Block diagram – State diagrams and state tables – Finite state machines (FSM)
• Types of sequential circuits – Synchronous (clocked) – Asynchronous
• Memory elements – Latches – Flip-flops
• Registers and shift registers – Generic devices – Standard 7400-series devices
The Sequential Circuit Model
Figure 6.1
zi = g(x1,…,xn,y1,…,yr) for i = 1,…,m Yi = g(x1,…,xn,y1,…,yr) for i = 1,…,r
(x1,…,xn) – Input (z1,…,zm) – Output
(y1,…,yr) – Present State (state) (Y1,…,Yr) – Next State
Types of Sequential Circuits
• Synchronous (clocked) circuits
• Asynchronous – will not cover in CSE 2441
– Pulse mode
– Fundamental mode
State Tables and State Diagrams (Synchronous Circuits)
Present state
Input
(a) (b)
Input/output
Present state
Next state
y
x
Y/z
x/z
Nextstate/output
y
Y
Figure 6.2
Sequential Circuit Example (Finite State Machine Model)
• Given – Input sequence
x = 0110101100 – Starting state A
• The machine behaves as follows
• Response – Output sequence z = 0100110111 – Final state C
1/1
Presentstate
A C
B D
(a)
(b)
0 1
0/1
0/0
1/1
x/z
Input x
0/0
1/0 1/0
D/0
B/1C/1
A/0
C/1
A/0D/0
B/1
A
BC
D
0/1
Figure 6.3
t 0 1 2 3 4 5 6 7 8 9 10
x 0 1 1 0 1 0 1 1 0 0
y A D B A D B B A C C C
Y D B A D B B A C C C
z 0 1 0 0 1 1 0 1 1 1
Realization Using D Flip-Flops
Synchronous Sequential Circuits
zm
z1
yr
Clock
y1
Memory
Combinational
logic
...
...
......
xn
x1
Yr
Y1
• State changes occur in synchronization with the clock signal • Typical memory devices – D flip-flops, JK flip-flops
Types of Memory Elements
• Synchronous circuits – D flip-flop
– JK flip-flop
– SR flip-flop
– T flip-flop
• Asynchronous circuits – Delay line (propagation delay)
– SR latch
– D latch
Set-Reset (SR) Latch
• Basic bistable, unclocked memory element
• Uses -- Memory in asynchronous circuits, component in clocked flip-flops
Characteristic Equation Q* = S + R’Q
Basic Clock Signal Terminology
Positive edge – low to high transitions Negative edge – high to low transitions Clock period (tc) – time between two positive edges. Clock cycle – same as clock period. Duty cycle -- % of cycle that is in a high state (50% in above case) Clock frequency – 1/tc
Positive edge Negative edge
|-Clock period-|
SN7474 – Dual Positive Edge-Triggered D Flip-Flop
Figure 6.23
Figure 6.28
Characteristic equation – Q* = D
SN7476 – Dual Pulse-Triggered JK Flip-Flop
Figure 6.27
Figure 6.25
Characteristic equation Q* = K’Q + JQ’
Generic Shift Register
Parallel in (Y)
Parallel out (X)
Serial outSerial in
Preset control
Shift pulse
Clear control
(a)
n-Bit shiftregister
Parallel in (Y)
Serial out
Preset control
Shift pulse
Clear control
(b)
n-Bit shiftregister
Parallel out (X)
Serial in
Shift pulse
Clear control
(c)
n-Bit shiftregister
Basic Register
Basic Serial-In/Serial-Out Register
Four-Bit Shift Register Example
D
C
S
R
Q
Q
D
C
S
R
Q
Q
D
C
S
R
Q
Q
D
C
S
R
Q
Q
+5V
O3
IN
SHIFT
CLEAR
O2O1 O4
SHIFT t0 t1 t2 t3 t4 t5 t6 t7 t8
IN 1 1 1 1 0 0 0 0 0
O1 0 1 1 1 1 0 0 0 0
O2 0 0 1 1 1 1 0 0 0
O3 0 0 0 1 1 1 1 0 0
O4 0 0 0 0 1 1 1 1 0
SN74491A Serial-in, Serial-out Shift Register
Clock
S
(9)
(12)
(11)
Q
R
(a)
CKQ
H
QH
Q
S Q
R
CK
Q
S Q
R
CK
Q
S Q
R
CK
Q
S Q
R
CK
Q
S Q
R
CK
Q
S Q
R
CK
Q
S Q
R
CK
Q
(13)
(14)
(b)
A B QH
HL´
H´L
HLL
LHH
tn = Reference bit time, clock low
tn + 8 = Bit time after 8 low-to-high clock transitions
NC
VCC
QH
QH
A
B
GND
NC
Clock
Inputs
at tn
Outputs
at tn + 8
QH
NC
NC
NC
NC
NC
(c)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AB
SN74164 Serial-in, Serial/Parallel-out Shift Register
SN74164 Function Table and Package
(c)
A
QC
VCC
QH
QG
QF
QE
B
QA
QB
QD
GND
(d)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A B
Inputs Outputs
LHHHH
´L
´´HL´
´´H´L
LQB0
QAn
QAn
QAn
LQA0
HLL
LQH0
QGn
QGn
QGn
QA0, QB0, QH0 = levels of QA, QB, QH, respectively,before the indicated steady-state input conditions are established.QAn, QGn = levels of QA, QG, respectively, before the mostrecent transition of the clock (1-bit shift)
Clock
Clear
ClockClear QA QB QHÉ
Serial Adder Unit
Preset
Shift
Clear
Carry delay
Fulladder
FA
X
Y
Z
ci-1
xi
yi
ci
si
n-Bit shiftregister
CLR
n-Bit shiftregister
n-Bit shiftregister
D
C
Q
Serial Accumulator
Preset
0
Clear
FA
CLR
X
Z
n-Bit shiftregister
D
CK
Q
ci
si
n-bit shiftregister
Shift
Serial out
(a)
Y
Parallel Accumulator
FA
CLR
D
CK
Q
...
...
...
FA
CLR
D
CK
Q
HA
CLR
D
CK
Q
(b)
xn x2 x1
z1z2zn
ClearAccumulate
zn+1
Introduction to Counters
• Counters – sequential circuits that tally, or count, in a predetermined code sequence, the number of input pulses received, e.g., 3-bit binary counter.
y2y1y0
Recall How A JK Flip-flop Works
Synchronous Binary Counter
CLR
J
CK
Q
Q
CK
K
CLR
J
CK
Q
KQ
CLR
J
CK
Q
KQ
CLR
J
CK
Q
KQ
...
...
...
Overflow
Xn
X1
X2
X3
Clear
Count
Inhibit(a)
(b)
00000
00001
00110
01010
11001
11000
11000
1
01010
Xn
X1
X2
X3
Recycles
X4 X3 X2 X1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Figure 7.11
SN74163 Synchronous Binary Counter
Synchronous clearSynchronous load
CountHoldHold
Load
Data A
Data B
Data C
Data D
(a)
(b)
(9)
(3)
(4)
(2)
(5)
(6)
(1)
(7)
Clock
ENP
ENT
Inputs
Mode
(10)
QAJ
K
LHHHH
´LHHH
´´HL´
´´H´L
Q
CK
(14)
QBJ
K
Q
CK
(13)
QCJ
K
Q
CK
(12)
RCO
J
K
Q
CK
(15)
QD(11)
Clear
Load ENPENTClear
Figure 7.12
SN74163 Timing Diagram
(c)
Clear
Load
Outputs
A
B
C
D
Clock
ENP
ENT
RCO
QA
QB
QC
QD
Syncclear
Syncload
Datainputs
12 13 14 15 0 1 2
Count Inhibit
Figure 7.12, con’t
Asynchronous Down Counter
CLR
J
CK
Q
Q
CK
K
CLR
J
CK
Q
KQ
CLR
J
CK
Q
KQ
...
...
...
Xn X1X2
Clear
(a)
(b)
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
...
...
...
...
...
...
Xn X1X2X3...
Clock
Count
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
...
...
...
...
...
...
Xn X1X2X3...
Up count mode Down count mode
Figure 7.16
Synchronous Up/Down Counter
CLR
J
CK
Q
Q
CK
K
...
Xn
Upoverflow
Downoverflow
CLR
J
CK
Q
Q
CK
K
X2
...
...
...
...
...
CLR
J
CK
Q
Q
CK
K
X1
Up/down
Clock
Clear
1
Figure 7.17
Modulo-N Counters – Counters that count from 0 to N-1 and repeat
• SN74160 Synchronous Decade Counter – counts 0 to 9
M1
Clear
D
VCC
QA
QB
QC
QD
Load
ENT
A
B
ENP
GND
(a)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
(1)
(9)
(10)
(7)
(2)
(3)
(4)
(5)
(6)
(b)
(14)
(13)
(12)
(11)
(1)
(2)
(4)
(8)
(15)
Clock
C
RCO
Clear
D
A
B
ENP
Load
C
Clock
ENT
QA
QB
QC
QD
RCO3CT = 9M2
CT = 0
G4
G5/2,3,4+
G3
CTRDIV 10
'160
1,5D
SN74160 Logic Diagram
Load
Data A
Data B
Data C
Data D
(c)
(9)
(3)
(4)
(2)
(5)
(6)
(1)
(7)
Clock
ENP
ENT(10)
QAJ
K
Q
CK
(14)
QBJ
K
Q
CK
(13)
QCJ
K
Q
CK
(12)
RCO
J
K
Q
CK
(15)
QD(11)
Clear
CLR
CLR
CLR
CLRQ
SN74160 Timing Diagram
(d)
Clear
Load
Outputs
A
B
C
D
Clock
ENP
ENT
RCO
QA
QB
QC
QD
Asyncclear
Syncload
Datainputs
7 8 9 0 1 2 3
Count Inhibit
Digital Timer Block Diagram
Minutes Seconds
Clear
1 Pulse/hour 1 Pulse/minute
1 Pulse/second
Power line
Start/Stop
¸
6
¸
10
¸
6
¸
10
¸
5
¸
12
Pulsegenerator
Figure 7.22
Recall D Flip Flop Functionality
Four-Bit Shift Register Example
D
C
S
R
Q
Q
D
C
S
R
Q
Q
D
C
S
R
Q
Q
D
C
S
R
Q
Q
+5V
O3
IN
SHIFT
CLEAR
O2O1 O4
SHIFT t0 t1 t2 t3 t4 t5 t6 t7 t8
IN 1 1 1 1 0 0 0 0 0
O1 0 1 1 1 1 0 0 0 0
O2 0 0 1 1 1 1 0 0 0
O3 0 0 0 1 1 1 1 0 0
O4 0 0 0 0 1 1 1 1 0
Four-Bit Ring Counter Example
SHIFT t0 t1 t2 t3 t4 t5 t6 t7 t8
O1 1 0 0 0 1 0 0 0 1
O2 0 1 0 0 0 1 0 0 0
O3 0 0 1 0 0 0 1 0 0
O4 0 0 0 1 0 0 0 1 0
Four-Bit Twisted-Ring Counter
SHIFT t0 t1 t2 t3 t4 t5 t6 t7 t8
IN 1 1 1 1 0 0 0 0 1
O1 0 1 1 1 1 0 0 0 0
O2 0 0 1 1 1 1 0 0 0
O3 0 0 0 1 1 1 1 0 0
O4 0 0 0 0 1 1 1 1 0
