Digital Logic and Design 10

8/10/2019 Digital Logic and Design 10

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Digital Logic and Design (EEE-241)Lecture 10

Dr. M. G. Abbas Malik. . .

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Analysis of Combinational Logic

Design of multilevel NAND combinational circuits Analysis of multilevel NAND combinationalc rcu s

Design of multilevel NOR combinational circuitsna ys s o mu eve com na ona c rcu s

Howe work:

-Equivalence logic circuits

Dr. M. G. Abbas Malik COMSATS Lahore2


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Combinational Circuit CostnayssGiven two circuits that perform the same function:

effective.This is not necessarily true when Integrated CircuitsIC are used

Since several gates are included in a single ICpackage, it becomes economical to use as manygates from an already used package even if, by doingso, we increase the total number of gates.Some of the interconnections among gates ICs areinternal to the chip.It is economical to use as many internal connectionsas possible to minimize the number of wires betweenexternal pins of ICs.



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In several occasions, the classical method will not

function.Truth Table simplification becomes too cumbersome if

With Integrated Circuits , it is not the count of gates

that determines the cost but the number and types ofICs em lo ed and the number of external interconnections needed to implement the givenBoolean function.In man cases the a lication of an alternate desi nprocedure can produce a combinational circuit for agiven function that is far better than the one obtainedby the classical design method.



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The classical method constitutes a general procedure

, , .

Before going through a detailed design of acombinational circuit, one should look whether the

SSI Small-scale Integration

MSI Medium-scale IntegrationLSI Lar e-scale Inte ration In this lecture, we will study examples ofcombinational circuits designed by methods otherthan the classical rocedure.

All of the examples demonstrate the internalconstruction of existing MSI.



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The full-adder forms the sum of two bits and aprevious carry.Two binary numbers of n bits each can be added

.When pair of bits are added through the full-adder,

pair of bits one higher significant position



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The bits are added with full-adders, starting fromthe least significant position, to form the sum bitand carry bit.

- ,can be generated in two ways: either in serialfashion or in arallel .The serial addition method uses only one full-adder circuit and a storage device to hold the

generated output carry and sum.The parallel method uses n full-adder circuits.



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A binary parallel adder is a digital function thatproduces the arithmetic sum of two binarynumbers in parallel.

-



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An n-bit parallel adder requires n full-adders

It can be constructed from 4-bit, 2-bit and 1-bitfull-adders ICs by cascading several packages.e - nary para e a er s a yp ca

example of an MSI function.

arithmetic operations.The a lication of this MSI function to the desi nof a combinational circuit is demonstrated in theexample of BCD to excess-3 code converter .



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Example: BCD to excess-3 code converter

A = BCS Code



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Carry Propagation

that all the bits of the augend and the addend areavailable for computation at the same time.

,propagate through the gates before the correct output

sum is available in the output terminals. delay of a typical gate times the number of gate levelsin the circuit.

is the time it takes the carry to propagate through thefull-adders



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Carry Propagation

The number of gate levels for the carrypropagation can be found from the circuit of the

The signal from the Carry (Ci) to the output carry



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Carry Propagation

If there are four full-adders in the parallel adder, theoutput carry C 5 would have 2 4 = 8 gate levels fromC to C .The total propagation time in the adder would be the

propagation time in one half adder plus eight gateeve sFor an n-bit parallel adder, there are 2n gate levels

The carry propagation time is a limiting factor on thespeed with which two numbers are added in parallel.



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Carry Propagation

-

If we define two variables:P i = A i BiG i = A iBi

G i is called a carry generate and it produces an outputcarry when both Ai and Bi are one.P i is called a carry propagate because it is the termassociated with the propagation of the carry C i to C i+1The out ut sum and carr can be ex ressed as:

S i = P i C iC i+1 = G i + P iC i



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Carry Propagation

Look-ahead CarryThe Boolean functions for the carry output of eachs age are:



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Carry Propagation

Look-ahead CarryCircuit diagram of a look-ahead carry generator



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4-bit Full-adders with Look-ahead carry



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Computers or calculators that perform arithmetic

represent decimal numbers in binary-coded form. An adder for such a computer must employ arithmetic

numbers and present results in the accepted code. A decimal adder requires a minimum of nine inputsand five out uts : Inputs

Four bits are required to code each decimal digit (8)One in ut carr 1

OutputsFour bits to represent the output decimal digit (4)One bit for out ut carr 1



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To design a 9-input, 5-output combinational circuit

y e c ass ca me o requ res a ru a e w29 = 512 entries.Man of the in ut combinations are Dont Care conditions.

An alternate procedure is to add the numbers- ,the fact that six combinations in each 4-bit inputare not used.

The output must be modified so that VALID binarycombinations of the decimal code are generated



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Consider the arithmetic addition of two decimaldigits in BCD, together with a possible carry froma previous stage.

,sum cannot be greater than

9+9+1 in ut carr =19If we apply two BCD digits to a 4-bit binary adder,the adder will form the sum in binary and

produced a result in a range from 0 to 19.0 0 0 11 0 0 1


---------

1 0 0 1 1


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Output of 4-bit adder Binary Sum BCD SumDecimal

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1

0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 2

0 0 0 1 1 0 0 0 1 1 3

0 0 1 0 1 0 0 1 0 1 5

0 0 1 1 0 0 0 1 1 0 6

0 0 1 1 1 0 0 1 1 1 7

0 1 0 0 0 0 1 0 0 0 8

0 1 0 0 1 0 1 0 0 1 9

0 1 0 1 0 1 0 0 0 0 10

0 1 0 1 1 1 0 0 0 1 11

0 1 1 0 0 1 0 0 1 0 12

0 1 1 0 1 1 0 0 1 1 13

0 1 1 1 0 1 0 1 0 0 14

0 1 1 1 1 1 0 1 0 1 15

1 0 0 0 0 1 0 1 1 0 16

1 0 0 0 1 1 0 1 1 1 17

1 0 0 1 0 1 1 0 0 0 18


1 0 0 1 1 1 1 0 0 1 19


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When the binary sum is equal to or less than 1001,

e correspon ng sum s en ca .When binary sum is greater than 1001, we obtain an

A correction of BCD is need when the binary sum has

an output carry K = 1. The other six combinationsfrom 1010 to 1111 that need a correction has Z 8 = 1and further more either Z 4 or Z 2 must be 1.

= + + When C = 1, it is necessary to add 0110 to the binarysum and provide an output carry for the next stage.



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A BCD adder is a circuit that adds two BCD digitsin parallel and produces a sum digit in BCD and acarry.

its internal construction.

,4-bit binary adder.



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A BCD adder can be constructed with three ICpac ages

2 MSI package: 2 4-bit adders1 SSI acka e: three ates for the correction lo ic

To achieve shorter propagation delay, an MSI

BCD adder includes the necessary circuits for- . A Decimal parallel adder that adds n decimaldigits needs n BCD adder stages. The output

carry from one stage must be connected to theinput carry of the next higher-order stage.



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Chapter 5: Section 5-4

Magnitude Comparator


Digital Logic and Design 10

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