ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg

Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg

Lecture 6

هــ 1438ذو الحجة

Winter 2017

Following the slides of Dr. Ahmed H. Madian

COURSE OUTLINE

1. Introduction

2. Gate-Level Minimization

3. Combinational Logic

4. Synchronous Sequential Logic

5. Registers and Counters

6. Memories and Programmable Logic

2

LECTURE OUTLINE

• Sequential Circuits • Introduction • Memory Types • Latches • SR Latch • D Latch

• Flip flops • Master-Slave SR and D flip-flops • Edge-Triggered D, JK and T flip-flops • Flip-flops: Representation

• Summary of Terminology

3

COMBINATIONAL LOGIC CIRCUITS

4

• These are circuits that use logic gates, where the output depends only on the current inputs

𝑤

𝑥

𝑦

𝑧

𝐹

SEQUENTIAL LOGIC CIRCUITS

5

• These are circuits where the outputs depend on the sequence of past outputs

• As a result, such a circuit must remember something about the past

Example: In a football game

• The current score = the previous goals (state) + new goal (input)

• For example, if you have a previous goal score of 5 and there is a new goal, then the final score will be 6

SEQUENTIAL LOGIC CIRCUITS

6

• A circuit with memory, whose outputs depend on the current input and the sequence of past outputs, is called a sequential circuit

• The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input

TYPES OF SEQUENTIAL LOGIC CIRCUITS

7

1. Synchronous, where the behavior of the circuit depends on the input signal at discrete instances of time (also called clocked)

2. Asynchronous, where the behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change

• A combinational logic circuit with feedback

STORAGE ELEMENTS

8

What is required from a storage element?

• Store data (hold)

• Accept writing new data (write)

• Read the stored data

TYPES OF STORAGE ELEMENTS

9

• Latches

• SR

• D

• Flip-flops

• Master-slave

• Edge-triggered

• D

• JK

• T

Before going in detail regarding storage elements, we must understand what a

clock signal is…

DEFINING THE CLOCK

10

• A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized to coordinate actions of circuits

• A clock signal is produced by a clock generator

• While other more complex arrangements are also in use, the most common clock signal takes the form of a square wave, with 50% duty cycle, usually with a fixed, constant frequency

• Circuits using a clock signal for synchronization may become active at either the rising or the falling edge of a clock cycle

Clk

CLOCK PULSES

11

• A clock pulse can be positive or negative

Positive pulse Negative pulse

Positive

edge

Negative

edge

Negative

edge

Positive

edge

BASIC MEMORY ELEMENTS

12

• A basic memory element consists of two cascaded inverters and the output of the last inverter is fed back into the input of the first inverter

• 𝑄 and 𝑄′ are the outputs of the memory element

• Such a memory element will always store a single bit

• Such a memory element is called a Latch

𝑄′ = 0 𝑄 = 1 1

STORAGE ELEMENTS

13

• But how to write a new value in this latch?

• We need a special technique that enables us to do this writing action

𝑄′ = 0 𝑄 = 1 1

𝑆𝑅 LATCH USING NOR GATES

14

𝑅

𝑆 𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑺

𝑹

𝑸

𝑸′

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

𝑆𝑅 LATCH USING NOR GATES

15

• The 𝑆𝑅 latch is constructed with two cross-coupled NOR gates and two inputs labelled 𝑆 for set and 𝑅 for reset

• The 𝑆𝑅 latch has two useful states

• When the output 𝑄 = 1 and 𝑄′ = 0, the latch is said to be in the set state

• When 𝑄 = 0 and 𝑄′ = 1, it is in the reset state

• Outputs 𝑄 and 𝑄′ are normally the complement of each other

𝑆𝑅 LATCH USING NOR GATES

16

• The 𝑆𝑅 latch can store only 1 bit

• If both inputs are equal to 1 at the same time, a condition in which both new outputs are equal to 0 occurs (irrespective of the old output values)

• If both inputs are then switched to 0 simultaneously, the device will enter an undefined state

In practice, setting both inputs to 1 is forbidden!

𝑆𝑅 LATCH USING NOR GATES

17

𝑅

𝑆 𝑄′

𝑄

• Writing a 1 into the memory cell – set state

1

1 0

0

0 1

𝑆𝑅 LATCH USING NOR GATES

18

𝑅

𝑆 𝑄′

𝑄

• Hold the written data in the memory cell – hold state

1

1 0

0

0 0

𝑆𝑅 LATCH USING NOR GATES

19

𝑅

𝑆 𝑄′

𝑄

• Writing a 0 into the memory cell – reset state

0

0 1

1

1 0

𝑆𝑅 LATCH USING NOR GATES

20

𝑅

𝑆 𝑄′

𝑄

• Hold the written date in the memory cell – hold state

0

0 0

1

1 0

𝑆𝑅 LATCH USING NOR GATES

21

• Having both inputs equal to 1 in the memory cell – forbidden state

• Because if 𝑆 and 𝑅 go to the hold state after being both equal to 1, the memory cell will go into an undefined state

𝑅

𝑆 𝑄′

𝑄 0

1

1 1

0

0

𝑆𝑅 LATCH USING NOR GATES

22 𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝑅

𝑆

𝑄

𝑄′

𝑆𝑅 LATCH USING NAND GATES

23

𝑆

𝑅 𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑺

𝑹

𝑸

𝑸′

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

Also known as the 𝑆′𝑅′ latch

𝑆𝑅 LATCH USING NAND GATES

24

• The outputs of the latch are 𝑄 and 𝑄′

• After each write operation there must be a hold operation to store the data

• Writing a 1 into the cell means set (𝑆 = 0 & 𝑅 = 1)

• The hold state means store the data (𝑆 = 𝑅 = 1)

• Writing a 0 into the cell means reset (𝑅 = 0 & 𝑆 = 1)

• For 𝑆 = 𝑅 = 0, this is an unstable condition

• The 𝑆′𝑅′ latch (𝑆𝑅 latch using NAND gates) can store only one bit

𝑆𝑅 LATCH: IMPLEMENTATION COMPARISON

𝑆

𝑅 𝑄′

𝑄

𝑺

𝑹

𝑸

𝑸′

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

𝑆

𝑅

𝑄′

𝑄

𝑺

𝑹

𝑸

𝑸′

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0 Forbidden case

set

hold

hold

reset set

hold

hold

reset

GATED 𝑆𝑅 LATCH USING NAND GATES

26

𝑅

𝑆

𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒

𝑬𝒏 𝑺 𝑹 Next state

of 𝑸

0 X X No change

1 0 0 No change

1 0 1 𝑄 = 0

1 1 0 𝑄 = 1

1 1 1 Undefined

𝐸𝑛

Can we hold (store) the value at the

outputs unchanged, even if the

inputs keep changing?

GATED 𝑆𝑅 LATCH USING NAND GATES

27

• The control input 𝐸𝑛 acts as an enable signal for the other two inputs

• The outputs of the first two NAND gates stay at the logic-1 level as long as the enable signal remains at 0

• When the enable input goes to 1, information from 𝑆 or 𝑅 input is allowed to affect the latch

• The set state is reached with 𝑆 = 1, 𝑅 = 0 and 𝐸𝑛 = 1

• The reset state is reached with 𝑆 = 0, 𝑅 = 1 and 𝐸𝑛 = 1

• In either case, when 𝐸𝑛 returns to 0, the circuit remains in its current state, irrespective of any later changes to 𝑆 or 𝑅

• An undefined condition occurs when 𝑆 = 𝑅 = 𝐸𝑛 = 1. As this places 0s on both inputs of the basic 𝑆𝑅 latch, which puts in in the undefined state

𝐷 LATCH (TRANSPARENT LATCH)

28

• Forces 𝑆 and 𝑅 to be complements of each other (so that they are never equal to 1 at the same time)

𝐷

𝐸𝑛

𝑄

𝑄′

𝐷 LATCH (TRANSPARENT LATCH)

29

• Forces 𝑆 and 𝑅 to be complements of each other (so that they are never equal to 1 at the same time)

𝑬𝒏 𝑫 Next state

of 𝑸

0 X No change

1 0 𝑄 = 0

1 1 𝑄 = 1

𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝐷 LATCH (TRANSPARENT LATCH)

30

• The D latch receives that designation from its ability to hold data in its internal storage

• It is suited for use as a temporary storage for binary info between a unit and its environment

• The binary information present at the data input of the D latch is transferred to the 𝑄 output when the enable input is asserted (𝐸𝑛 = 1)

• The output follows changes in the data input as long as the enable input is asserted (𝐸𝑛 = 1)

• This situation provides a path from input D to the output (thus the naming transparent latch)

• When the enable input is de-asserted (𝐸𝑛 = 0), the binary info that was present at the data input at the time the transition occurred is stored

THE LATCH TIMING PROBLEM

31

• What happens if 𝐶𝑙𝑘 = 1? What will be the value of 𝑄 when the 𝐶𝑙𝑘 goes to 0?

• Problem: A latch is transparent, its state keeps changing as long as the clock remains active

• Due to this uncertainty, latches cannot be reliably used as storage elements

THE LATCH TIMING PROBLEM

32

• When latches are used as storage elements, a problem arises

• The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level

• The new state of a latch appears at the output while the pulse is still active

• This output is connected to the inputs of the latches through the combinational circuit

• If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur

THE LATCH TIMING PROBLEM

33

• This is an unpredictable situation, since the state of the latches may keep changing as long as 𝐶𝑙𝑘 = 1

• Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source

FLIP-FLOPS

34

• A flip-flop is a one-bit memory cell, similar to latches

• A flip-flop solves the issue of latch transparency

• Latches are level sensitive memory elements (active as long as 𝐶𝑙𝑘 = 1)

• Flip-flops are edge-triggered or edge-sensitive memory elements (active only at transitions; i.e. either 0 → 1 or 1 → 0)

RESPONSE OF LATCHES VS. FLIP-FLOPS

Flip-flop

Flip-flop

Latch

35

LEVEL-SENSITIVE VS. EDGE-TRIGGERED STORAGE ELEMENTS

36

𝐶𝑙𝑘

𝐷

𝑄𝑎

𝑄𝑏

𝑄𝑐

𝐷

𝐶𝑙𝑘

𝑄𝑎

𝑄𝑎′

𝑄𝑏

𝑄𝑏′

𝑄𝑐

𝑄𝑐′

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚 𝐶𝑖𝑟𝑐𝑢𝑖𝑡

FLIP-FLOP TYPES

37

• The commonly-used solution replaces the controlled D latch with a flip-flop

• We have two types of flip-flops

• Master-slave

• Edge-triggered

𝑄

𝑌

𝐷

MASTER-SLAVE 𝐷 FF USING LATCHES

38

𝑄 𝑌 𝐷

𝐶𝑙𝑘

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝐶𝑖𝑟𝑐𝑢𝑖𝑡

𝐶𝑙𝑘

MASTER-SLAVE 𝐷 FF USING LATCHES

39

𝑄 𝑌 𝐷

𝐶𝑙𝑘

• The circuit samples the 𝐷 input and changes its output 𝑄 only at the negative edge of the synchronizing or controlling clock

• When 𝐶𝑙𝑘 = 0, the output of the inverter is 1

• The slave latch is enabled and its output 𝑄 is equal to the master output 𝑌

• The master latch is disabled because 𝐶𝑙𝑘 = 0

𝐶𝑖𝑟𝑐𝑢𝑖𝑡

MASTER-SLAVE 𝐷 FF USING LATCHES

40

𝑄 𝑌 𝐷

𝐶𝑙𝑘

• When the input pulse changes to the logic-1 level, the data from the external 𝐷 is transferred to the master. The slave, however, is disabled as long as the clock remains at the logic-1 level, because its enable input is equal to 0

• Any change in the input changes the master output at 𝑌, but cannot affect the slave output

𝐶𝑖𝑟𝑐𝑢𝑖𝑡

MASTER-SLAVE 𝐷 FF USING LATCHES

41

𝑄 𝑌 𝐷

𝐶𝑙𝑘

• The value that is produced at the output of the flip-flop is the value that was stored in the master stage immediately before the negative edge occurred

How to design a similar master-slave D flip-flop such that the

output changes on the positive edge of the clock?

𝐶𝑖𝑟𝑐𝑢𝑖𝑡

EDGE-TRIGGERED 𝐷 FLIP-FLOP

42

• Sensitive to inputs only near the edge of the clock signal (not while high)

• ↑ signifies a positive edge 𝑸(𝒕) 𝑫 𝑪𝒍𝒌 𝑸 𝒕 + 𝟏

0 0 ↑ 0

0 1 ↑ 1

1 0 ↑ 0

1 1 ↑ 1

𝑄𝑝𝑜𝑠 𝑄𝑛𝑒𝑔

𝑄𝑝𝑜𝑠′ 𝑄𝑛𝑒𝑔

′

EDGE-TRIGGERED 𝐷 FLIP-FLOP

43

• Sensitive to inputs only near the edge of the clock signal (not while high)

• This timing diagram is for a positive edge triggered 𝐷 flip-flop

𝐶𝑙𝑘

𝐷

𝑄

𝑄′ 𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝐽𝐾 FLIP-FLOP USING 𝐷 FLIP-FLOP

44

𝑄

𝑄′

𝐽

𝐾

• 𝑄 𝑡 + 1 = 𝐷 = 𝐽𝑄′ + 𝐾′𝑄

• When 𝐽 = 𝐾 = 1, the output is complemented

𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙 𝐶𝑖𝑟𝑐𝑢𝑖𝑡

• 𝐽 sets the flip-flop to 1

• 𝐾 resets the flip-flop to 0

𝐶𝑙𝑘

𝑇 FLIP-FLOP USING 𝐽𝐾 FLIP-FLOP

45

𝑇

• 𝑄 𝑡 + 1 = 𝐷 = 𝑇 ⊕ 𝑄

• 𝑇 (toggle) flip-flop is a complementing flip-flop

𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙 𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝑓𝑜𝑟𝑚 𝐽𝐾 𝐹𝐹

• 𝑇 = 0, no change

• 𝑇 = 1 , complement (toggle)

𝑄

𝑄′

𝑇 FF USING 𝐷 FF

46

𝑇

• 𝑄 𝑡 + 1 = 𝐷 = 𝑇 ⊕ 𝑄

• 𝑇 (toggle) flip-flop is a complementing flip-flop

𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙 𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝑓𝑜𝑟𝑚 𝐷 𝐹𝐹

• 𝑇 = 0, no change

• 𝑇 = 1 , complement (toggle)

FLIP-FLOPS: REPRESENTATION

47

• To represent any combinational circuit, we needed to write the truth table or logic function of the output

• To represent any flip-flop, we need to write the characteristic table, characteristic equation or excitation table

• A characteristic table defines the operation of a FF in a tabular form

• The next state is defined in terms of the current state and the inputs

• 𝑄(𝑡) refers to the current state (before the clock arrives)

• 𝑄(𝑡 + 1) refers to the next state (after the clock arrives)

• Similar to the truth table in combinational circuits

FLIP-FLOPS: REPRESENTATION

48

• A characteristic equation defines the operation of a flip-flop in an algebraic form

• For a 𝐷 flip-flop: 𝑄 𝑡 + 1 = 𝐷

• For a 𝐽𝐾 flip-flop: 𝑄 𝑡 + 1 = 𝐽𝑄′ + 𝐾′𝑄

• For a 𝑇 flip-flop: 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄

49

𝑄 𝑡 + 1 = 𝐷 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄

𝑄 𝑡 + 1 = 𝐽𝑄′ + 𝐾′𝑄

FLIP-FLOPS: EXCITATION TABLES

50

• If we have the present and next output, what would be the input to the flip-flop that would lead to this output?

𝑸(𝒕) 𝑸(𝒕 + 𝟏) 𝑱 𝑲 𝑻 𝑫

0 0 0 𝑋 0 0

0 1 1 𝑋 1 1

1 0 𝑋 1 1 0

1 1 𝑋 0 0 1

STANDARD SYMBOLS FOR STORAGE ELEMENTS

51

Edge-Triggered Flip-flops

Master-Slave Flip-flops

Latches

DIRECT INPUT (ASYNCHRONOUS INPUT)

52

• An example of an asynchronous sequential circuit is a counter circuit that counts the number of occurrences of some event

• Such a circuit is usually built using a number of flip-flops, whose outputs are interpreted as a number

• The counter circuit should be able to increment or decrement the number

• It is also important to be able to force the counter into a known initial state (𝑐𝑜𝑢𝑛𝑡 = 0), which means that all flip-flops must have 𝑄 = 0

• Moreover, we should be able to preset each flip-flop to 𝑄 = 1, to insert some specific count as the initial value in the counter

DIRECT INPUT (ASYNCHRONOUS INPUT)

53

• These requirements can all be satisfied by incorporating a Clear and Preset inputs into the design of a flip-flop

• These extra inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the 𝐶𝑙𝑘 signal

𝑁𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑒𝑑𝑔𝑒 − 𝑡𝑟𝑖𝑔𝑔𝑒𝑟𝑒𝑑 𝐷 𝑓𝑙𝑖𝑝 − 𝑓𝑙𝑜𝑝 𝑤𝑖𝑡ℎ 𝐶𝑙𝑒𝑎𝑟 𝑎𝑛𝑑 𝑃𝑟𝑒𝑠𝑒𝑡

SUMMARY OF TERMINOLOGY

54

• A basic latch is a feedback connection of two NOR gates or two NAND gates, which can store one bit of information. The NOR-based latch can be set to 1 using the 𝑆 input and reset to 0 using the 𝑅 input

• A gated (clocked) latch is a basic latch that includes input gating and a control input signal. The latch retains its existing state when the control input is equal to 0. Its state may be changed when the control signal is equal to 1. We referred to this control input as the clock

• A gated (clocked) SR latch uses the 𝑆 and 𝑅 inputs to set the latch to 1 or reset it to 0, respectively

• A gated (clocked) D latch uses the input 𝐷 to force the latch into a state that has the same logic value as the 𝐷 input

SUMMARY OF TERMINOLOGY

55

• A flip-flop is a storage element based on the gated latch

principle, which can have its output state changed only on the

edge of the controlling clock signal

• A Master-slave flip-flop is built with two gated latches. The

master stage is active during half of the clock cycle, and the

slave stage is active during the other half. The output value of

the flip-flop changes on the edge of the clock that activates the

transfer into the slave stage

• An edge-triggered flip-flop is affected only by the input values

present when the active edge of the clock occurs