ELCT201: DIGITAL LOGIC DESIGN - GUC · 2020. 4. 13. · GATED LATCH USING NAND GATES 28 • The...

ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, [email protected]

Dr. Eng. Wassim Alexan, [email protected]

Lecture 7

هــ 1441محرم

Spring 2020

Following the slides of Dr. Ahmed H. Madian

mailto:[email protected]

COURSE OUTLINE

1. Introduction

2. Gate-Level Minimization

3. Combinational Logic

4. Synchronous Sequential Logic

5. Registers and Counters

6. Memories and Programmable Logic

2

LECTURE OUTLINE

• Sequential Circuits

• Introduction

• Memory Types

• Latches

• SR Latch

• D Latch

•Introduction to Flip-Flops

3

COMBINATIONAL LOGIC CIRCUITS

4

• These are circuits that use logic gates, where the output depends only on the current inputs

𝑤

𝑥

𝑦

𝑧

𝐹

SEQUENTIAL LOGIC CIRCUITS

5

• These are circuits where the outputs depend on the sequence of past outputs

• As a result, such a circuit must remember something about the past

Example: In a football game

• The current score = the previous goals (state) + new goal (input)

• For example, if you have a previous goal score of 5 and there is a new goal, then the updated score will be 6

SEQUENTIAL LOGIC CIRCUITS

6

• A circuit with memory, whose outputs depend on the current input and the sequence of past outputs, is called a sequential circuit

• The behavior of such a circuit may be described by a state table that specifies its output and next state as functions of its current state and input

TYPES OF SEQUENTIAL LOGIC CIRCUITS

7

1. Synchronous, where the behavior of the circuit depends on the input signal at discrete instances of time (also called clocked)

2. Asynchronous, where the behavior of the circuit depends on the input signals at any instance of time and the order of the inputs change

• A combinational logic circuit with feedback

STORAGE ELEMENTS

8

What is required from a storage element?

• Store data (hold)

• Accept writing new data (write)

• Read the stored data

TYPES OF STORAGE ELEMENTS

9

• Latches

• SR

• D

• Flip-flops

• Master-slave

• Edge-triggered

• D

• JK

• T

Before going in detail regarding storage elements, we must understand what a

clock signal is…

DEFINING THE CLOCK

10

• A clock signal is a particular type of signal that oscillates between a high and a low state and is utilized to coordinate actions of circuits

• A clock signal is produced by a clock generator

• While other more complex arrangements are also in use, the most common clock signal takes the form of a square wave, with 50% duty cycle, usually with a fixed, constant frequency

• Circuits using a clock signal for synchronization may become active at either the rising or the falling edge of a clock cycle

Clk

11 iPhone 11 Samsung Galaxy S20

Six-core CPU, with two high-

performance cores running at

2.65 GHz called Lightning and

four energy-efficient cores called

Thunder

Apple A13 Bionic

Octa-core (2x2.73 GHz

Mongoose M5 & 2x2.50 GHz

Cortex-A76 & 4x2.0 GHz

Cortex-A55)

Qualcomm SM8250 Snapdragon 865

CLOCK PULSES

12

• A clock pulse can be positive or negative

Positive pulse Negative pulse

Positive

edge

Negative

edge

Negative

edge

Positive

edge

BASIC MEMORY ELEMENTS

13

• A basic memory element consists of two cascaded inverters and the output of the last inverter is fed back into the input of the first inverter

• 𝑄 and 𝑄′ are the outputs of the memory element

• Such a memory element will always store a single bit

• Such a memory element is called a Latch

𝑄′ = 0 𝑄 = 1 1

STORAGE ELEMENTS

14

• But how to write a new value in this latch?

• We need a special technique that enables us to do this writing action

𝑄′ = 0 𝑄 = 1 1

𝑆𝑅 LATCH USING NOR GATES

15

𝑅

𝑆 𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑺

𝑹

𝑸

𝑸′

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

State Input

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


16

• The 𝑆𝑅 latch is constructed with two cross-coupled NOR gates and two inputs labelled 𝑆 for set and 𝑅 for reset

• The 𝑆𝑅 latch has two useful states

• When the output 𝑄 = 1 and 𝑄′ = 0, the latch is said to be in the set state

• When 𝑄 = 0 and 𝑄′ = 1, it is in the reset state

• Outputs 𝑄 and 𝑄′ are desired to normally be the complement of each other


17

• The 𝑆𝑅 latch can store only 1 bit

• If both inputs are equal to 1 at the same time, a condition in which both new outputs are equal to 0 occurs (irrespective of the old output values)

• If both inputs are then switched to 0 simultaneously, the device will enter an undefined state

In practice, setting both inputs to 1 is forbidden!


18

𝑅

𝑆 𝑄′

𝑄

• Writing a 1 into the memory cell – set state

1

1 0

0

0 1

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


19

𝑅

𝑆 𝑄′

𝑄

• Hold the written data in the memory cell – hold state

1

1 0

0

0 0

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


20

𝑅

𝑆 𝑄′

𝑄

• Writing a 0 into the memory cell – reset state

0

0 1

1

1 0

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


21

𝑅

𝑆 𝑄′

𝑄

• Hold the written date in the memory cell – hold state

0

0 0

1

1 0

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


22

• Having both inputs equal to 1 in the memory cell – forbidden state

• Because if 𝑆 and 𝑅 go to the hold state after being both equal to 1, the memory cell will go into an undefined state

𝑅

𝑆 𝑄′

𝑄 0

1

1 1

0

0

X Y NOR

0 0 1

0 1 0

1 0 0

1 1 0


23 𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝑅

𝑆

𝑄

𝑄′

𝑅 𝑆

1 0

𝑅 𝑆

0 0

𝑅 𝑆

0 1

𝑅 𝑆

0 0

𝑅 𝑆

1 0

𝑅 𝑆

1 1

𝑅 𝑆

1 0

𝑅 𝑆

0 0

𝑅 𝑆

0 1

𝑅 𝑆

1 1

𝑅 𝑆

0 0

𝑅

𝑆𝑄′

𝑄

𝑆𝑅 LATCH USING NAND GATES

24

𝑆

𝑅 𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑺

𝑹

𝑸

𝑸′

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

Also known as the 𝑆′𝑅′ latch State Input

X Y NAND

0 0 1

0 1 1

1 0 1

1 1 0

𝑆𝑅 LATCH USING NAND GATES

25

• The outputs of the latch are 𝑄 and 𝑄′

• After each write operation there must be a hold operation to store the data

• Writing a 1 into the cell means set (𝑆 = 0 & 𝑅 = 1)

• The hold state means store the data (𝑆 = 𝑅 = 1)

• Writing a 0 into the cell means reset (𝑅 = 0 & 𝑆 = 1)

• For 𝑆 = 𝑅 = 0, this is an unstable condition

• The 𝑆′𝑅′ latch (𝑆𝑅 latch using NAND gates) can store only one bit

𝑆𝑅 LATCH: IMPLEMENTATION COMPARISON

𝑆

𝑅 𝑄′

𝑄

𝑺

𝑹

𝑸

𝑸′

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

𝑆

𝑅

𝑄′

𝑄

𝑺

𝑹

𝑸

𝑸′

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0 Forbidden case

set

hold

hold

reset set

hold

hold

reset

27

𝑅

𝑆

𝑄′

𝑄

𝐶𝑖𝑟𝑐𝑢𝑖𝑡 𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒

𝑬𝒏 𝑺 𝑹 Next state

of 𝑸

0 X X No change

1 0 0 No change

1 0 1 𝑄 = 0

1 1 0 𝑄 = 1

1 1 1 Undefined

𝐸𝑛

This design allows

to hold (store) the

value at the

outputs

unchanged when

En=0, even if the

inputs keep

changing!

X Y NAND

0 0 1

0 1 1

1 0 1

1 1 0

GATED 𝑆𝑅 LATCH USING NAND GATES

𝑺

𝑹

GATED 𝑆𝑅 LATCH USING NAND GATES

28

• The control input 𝐸𝑛 acts as an enable signal for the other two inputs

• The outputs of the first two NAND gates stay at the logic-1 level as long as the enable signal remains at 0

• When the enable input goes to 1, information from 𝑆 or 𝑅 input is allowed to affect the latch

• The set state is reached with 𝑆 = 1, 𝑅 = 0 and 𝐸𝑛 = 1

• The reset state is reached with 𝑆 = 0, 𝑅 = 1 and 𝐸𝑛 = 1

• In either case, when 𝐸𝑛 returns to 0, the circuit remains in its current state, irrespective of any later changes to 𝑆 or 𝑅

• An forbidden condition occurs when 𝑆 = 𝑅 = 𝐸𝑛 = 1. As this places 0s on both inputs of the basic 𝑆𝑅 latch, which could lead to an undefined state upon further inputs

𝐷 LATCH (TRANSPARENT LATCH)

29

• Forces 𝑆 and 𝑅 to be complements of each other (so that they are never equal to 1 at the same time)

𝐷

𝐸𝑛

𝑄

𝑄′


30


𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙

𝑬𝒏 𝑺 = 𝑫 𝑹 = 𝑫′ Next state

of 𝑸

0 X X No change

1 0 0 No change

1 0 1 𝑄 = 0

1 1 0 𝑄 = 1

1 1 1 Forbidden


31


𝑬𝒏 𝑫 Next state

of 𝑸

0 X No change

1 0 𝑄 = 0

1 1 𝑄 = 1

𝐶ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐 𝑡𝑎𝑏𝑙𝑒 𝐺𝑟𝑎𝑝ℎ𝑖𝑐 𝑠𝑦𝑚𝑏𝑜𝑙


32

• The D latch receives that designation from its ability to hold data in its internal storage

• It is suited for use as a temporary storage for binary info between a unit and its environment

• The binary information present at the data input of the D latch is transferred to the 𝑄 output when the enable input is asserted (𝐸𝑛 = 1)

• The output follows changes in the data input as long as the enable input is asserted (𝐸𝑛 = 1)

• This situation provides a path from input D to the output (thus the naming transparent latch)

• When the enable input is de-asserted (𝐸𝑛 = 0), the binary info that was present at the data input at the time the transition occurred is stored

THE LATCH TIMING PROBLEM

33

𝐶𝑙𝑘

𝐷

𝑄

𝑄𝑏

𝑄𝑐

𝐶𝑙𝑘

𝐷

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

𝑄

𝑄′

Using Clk as enable for controlled Synchronous Operation is not Possible for D-Latch

As Long as Clk=1 the Latch output asynchronously follows input Data D


34

• When latches are used as storage elements, a problem arises

• The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level

• The new state of a latch appears at the output while the pulse is still active

• This output is connected to the inputs of the latches through the combinational circuit

• If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur


35

• This is an unpredictable situation, since the state of the latches may keep changing as long as 𝐶𝑙𝑘 = 1

• Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source

FLIP-FLOPS

36

• A flip-flop is a one-bit memory cell, similar to latches

• A flip-flop solves the issue of latch transparency

• Latches are level sensitive memory elements (active as long as 𝐶𝑙𝑘 = 1)

• Flip-flops are edge-triggered or edge-sensitive memory elements (active only at transitions; i.e. either 0 → 1 or 1 → 0)

RESPONSE OF LATCHES VS. FLIP-FLOPS

Flip-flop

Flip-flop

Latch

37

LEVEL-SENSITIVE VS. EDGE-TRIGGERED STORAGE ELEMENTS

38

𝐶𝑙𝑘

𝐷

𝑄𝑎

𝑄𝑏

𝑄𝑐

𝐷

𝐶𝑙𝑘

𝑄𝑎

𝑄𝑎′

𝑄𝑏

𝑄𝑏′

𝑄𝑐

𝑄𝑐′

𝑇𝑖𝑚𝑖𝑛𝑔 𝑑𝑖𝑎𝑔𝑟𝑎𝑚 𝐶𝑖𝑟𝑐𝑢𝑖𝑡

+ve Edge FF

-ve Edge FF

D-Latch

𝑄

𝑌

𝐷

MASTER-SLAVE 𝐷 FF USING LATCHES

39

𝑄 𝑌 𝐷

𝐶𝑙𝑘


𝐶𝑖𝑟𝑐𝑢𝑖𝑡

𝐶𝑙𝑘

Negative Edge D-FF

𝑄

𝑌

𝐷


40

𝑄 𝑌 𝐷

𝐶𝑙𝑘



𝐶𝑙𝑘

Negative Edge D-FF

𝑄

𝑌

𝐷


41

𝑄 𝑌 𝐷

𝐶𝑙𝑘



𝐶𝑙𝑘

Negative Edge D-FF

ELCT201: DIGITAL LOGIC DESIGN - GUC · 2020. 4. 13. · GATED LATCH USING NAND GATES 28 • The...

Documents

Transcript of ELCT201: DIGITAL LOGIC DESIGN - GUC · 2020. 4. 13. · GATED LATCH USING NAND GATES 28 • The...