Digital logic design 2
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DIGITAL LOGIC DESIGN II
Transcript of Digital logic design 2
DIGITALLOGIC DESIGN II
Logical Gates
AND Gate ConstructionTwo transistors are
connected in series using common collector configuration.
If both the inputs at A and B at the base of two transistors are high only then both the transistors will be on and output at the emitter will appear.
OR Gate ConstructionTwo common
collector transistors are connected in parallel.
If input appears high at either of the two transistors then output will appear.
Universal GateNAND and NOR Gates are called
Universal Gates because AND, OR and NOT gates can be created by using these gates.
NAND Gate Implementations
NOR Gate Implementations
10’s Complement9’s ComplementLet us take a decimal number 456,
9’s complement of this number will be9-4 = 59-5 = 49-6 = 3
9’s complement of 456 = 543Add 1 to get the 10’s Complement543 +1 = 544
2’S Complement Process The steps in the 2’s Complement process are similar to the 10’s Complement process. However, you will now use the base two. First, complement all of the digits in a number.
◦ A digit’s complement is the number you add to the digit to make it equal to the largest digit in the base (i.e., 1 for binary). In binary language, the complement of 0 is 1, and the complement of 1 is 0.
Second, add 1.
10
2’s Complement Examples
11
Example #1
Example #2
Complement Digits
Add 1
5 = 00000101
-5 = 11111011
11111010
+1
Complement Digits
Add 1
-13 = 11110011
13 = 00001101
00001100
+1
FUNCTIONS OF COMBINATIONAL LOGIC
Adder An ADDER tells the total number of 1s at the inputs
Let A=0 and B=0 then 0+0 = 0, (number of 1s is 0) Let A=0 and B=1 then 0+1 = 1, (number of 1s is 1) Let A=1 and B=0 then 1+0 = 1, (number of 1s is 1) Let A=1 and B=1 then 1+1= 10, (number of 1s is 2) When we add 1+1 the answer is 10 because decimal
1+1 = 2 and binary of 2 = 10. But the output of the OR gate will be 1 which is not the
right answer. The solution is a half-adder.
A
B
F
Binary AdditionWith the help of half adder, we can
design circuits that are capable of performing simple addition with the help of logic gates.
There are four possible combinations of single digit, two number addition:
0+0 = 00+1 = 11+0 = 11+1 = 10
Truth Table for Adding Two 1-Bit Numbers
INPUTS OUTPUTS
A B Q R
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Half-Adder The result is shown in a truth-table below. ‘SUM’
is the normal output and ‘CARRY’ is the carry-out.INPUTS OUTPUTSA B CARRY SUM 0 0 0 00 1 0 11 0 0 11 1 1 0
From the equation it is clear that this 1-bit adder can be easily implemented with the help of XOR Gate for the output ‘SUM’ and an AND Gate for the carry.
Hence A.B Carry BA Sum
Half-Adder Circuits
Exclusive OR Logic Circuit
Exclusive OR
Half-Adder LimitationIf we want to add 3 single digit
binary numbers then half-adder cannot perform it, because there are only two input ports.
We need 3 input ports to add 3 bits For that we use Full-Adder.
Full-AdderBy connecting two half-adders together, we can
add 3 single digit binary numbersWe need 3 input lines, one for each number.Two input lines feed into the first half adder;
the third input line functions as a carry-in line. The second half-adder has two input lines: the
output sum from the first half-adder, plus the third, carry-in input line.
Full Adder is used to add the output carry bit of the previous bits to next addition of the bits.
Full Adder can count the number of 1s upto three only.
In other words the maximum input bits are 3.
Full Adder Truth Table
Full-Adder Block Diagram
LSB bits are input through CARRY IN. MSB bits are input through Q. CARRY OUT of both the half adders is ORed. SUM is taken from the sum output of the second half adder.
CinBAABCoutCinBAS
)()(
Full Adder Circuit
Multi Bit AdditionLet’s move from adding 3 (or more)
single digit numbers to adding multi-bit numbers
First, note that the sum of adding two N-bit numbers can be N + 1 bits
This comes as a result of possibly obtaining a carry into the next column
Adding N-bit numbers isn’t an abstract consideration – it’s a real computing operation - at a minimum, a modern computer would add 16 bit numbers, done with a 16-bit adder
Multibit AdditionHere is the general rule: to add two
N-bit numbers, N full adders are required, one for each column in the sum
The first 2 inputs for each full adder come from the digits in the numbers to be added
The carry-out produced for each column is used as the carry-in for the next column to the left
At some point, you can have overflow as you exceed the adder circuitry capability.
2 Digit Adder A0 is the low order bit of A. A1 is the high order bit of A. B0 is the low order bit of B. B1 is the high order bit of B. Σ0is the low order bit of the sum. Σ1 is the high order bit of the sum. Cout is the Carry.
4 Digit Adder Two or more full-adders are added to form parallel binary
adders. Suppose we have two 4 digit binary numbers
X =X3 X2 X1 X0 and Y =Y3 Y2 Y1 Y0 then,4 bits full adder is as shown below
C0 is grounded because the there is no carry bit in the addition of first bits (LSBs)
Propagation DelayAll logic gates take a non-zero time
delay to respond to a change in input.This is the propagation delay of the
gate, typically measured in tens of nanoseconds.
X Y
time
X 1
0
Y 1
0
Propagation DelayThe propagation delay described above is
caused by parasitic capacitors inside the gates and the physical limitations of the devices used to build these gates.
Another cause of delay is the capacitor associated with the loads seen by a gate.
These capacitors are the result of the wiring (net delays) between gates (e.g. a long metal line connecting two gates on a chip) and the input capacitor of the gates as is shown in figure.
These capacitors need to be charged or discharged through the gate that drives them (e.g. gate 1 in Figure a).
The more capacitors that need to be charged or discharged the longer it will take for the output to change.
Also, the longer the interconnection, the more resistance the nets will have.
The easiest way to visualize this is to use a hydraulic equivalent of a capacitor and a resistor: a bucket filled with water and a narrow pipe, respectively, as shown in Figure b.
The more buckets connected to the drain, the longer it will take to empty them.
Carry Ripple in Parallel AdderThe carry input to each adder is the
carry output from the previous adder. Since the output of each adder
depends on the carry from the previous adder, each adder must "wait" for the carry output of the previous adder.
This carry ripple slows down the addition circuit, especially as the number of bits in the adder increases.
Carry RippleA and B inputs change, corresponding changes
to CIN inputs ‘ripple’ through the circuit.
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
B1 A1 B0 A0 B2 A2
CIN = 0
Q1 Q0 Q2
t = 0, A & B changet = 30 ns, Adder 0 outputs respondt = 60 ns, Adder 1 outputs respondt = 90 ns, Adder 2 outputs respond
Overflow Overflow occurs when the result of addition
does not fit in the representation being used. For example, if 4 bit unsigned numbers 6 =
0110 and 12 = 1100 are added the sum 18 overflows because maximum possible value for a 4 bit number is 15
Another Example: 6+4 using a three-bit adder.
(6)10 = (110)2 and (4)10 = (100)2
1 1 0 1 0 010 1 0
+
Binary SubtractionSubtraction Truth Table
0 – 0 = 010 – 1 = 111 – 1 = 10
Example:
Exercise: Subtraction 10 00 10 11 0 – 11 11 01 0
http://ryanstutorials.net/binary-tutorial/binary-arithmetic.php
1 1
Half SubtractorHalf Subtractor is used for
subtracting one single bit binary number from another single bit binary number.
Full SubtractorAs in the case of the addition using
logic gates, a full subtractor is made by combining two half-subtractors and an additional OR-gate.
A full subtractor has the borrow in capability (denoted as BORIN in the diagram below) and so allows cascading which results in the possibility of multi-bit subtraction.
Full Subtractor Circuit
Subtract B from A and C from the result of B-A
Carry Look Ahead AddersThe main idea behind carry look-
ahead addition is an attempt to generate all incoming carries in parallel and avoid waiting until the correct carry propagates from the previous full adder.
Carry Look Ahead Adder Look at a 3 bit truth table
In the red marked rows we get Cout =1 when either x =1 or y=1, provided Cin=1.
In the green rows we get Cout = 1 when both x=1 and y = 1, whether Cin = 1 or 0.
Carry Look Ahead AdderThis can be represented in logical
equations as below:
The above equation says that◦A carry is generated if both operand bits
are 1, irrespective of the fact that the previous carry was 1 or 0.
◦An incoming carry is propagated if one of the operand bits is 1 and the other is 0 and the previous carry bit is also 1.
GenerationThe addition of two 1-digit inputs A and B is said to generate if the addition will always carry, regardless of whether there is an input carry.We know that AND logic gives 1 only when both A and B are 1.
Hence Generation(A,B) = A.B
Propagate:The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry equal to 1.
In the case of binary addition, propagates if and only if at least one of A or B is 1.
Hence P(A,B) = A xor B
p3g2
g3
p3p2g1
p3p2p1g0
p3p2p1p0c0
Binary MultiplicationBinary multiplication uses the same
technique as decimal multiplication. Multiplication
Rule0 x 0 = 00 x 1 = 01 x 0 = 01 x 1 = 1
Binary MultiplicationConsider the simple problem of
multiplying 1102 by 102.
1 1 0 1 00 0 0
1 1 0 1 1 0 0
Binary Multiplication
2 bit Binary Multiplication
2-bit Binary Multiplier
HA HA
4 bit Binary Multiplier
Assignment Find the output of the 2-bit multiplier
ifA = 1 0 and B = 0 1A = 1 1 and B = 1 1
Find the output for 4-bit multiplier ifA = 1010 and B = 0011A = 1001 and B = 0110
Multiplication by Arrays A slightly different implementation scheme is shown in
the figure below. This multiplier is constructed from an array of building
blocks, shown in the figure below. Each building block consists of an AND gate for
computing locally the corresponding partial product (XYg), an input passed into the block from above (Sum In), and a carry (Cin) passed from a block diagonally above.
It generates a carry out bit (COUT) and a new sum out bit (Sum Out).
Binary DivisionCompare X (dividend) and Y (divisor).
a) If X >= Y, the quotient bit is 1 and perform the subtraction X-Y. b) If X < Y, the quotient bit is 0 and do not perform any subtractions.
Shift Y one bit to the right and compare X and Y.
Binary Division
110 is not subtracted from 111. 110 is just copied down as it is and 1 is added from the next digit
Binary DividerWe will consider the design of a
parallel divider for positive binary numbers.
As an example, we will design a circuit to divide an 8-bit dividend by a 4-bit divisor to obtain a 4-bit quotient.
8-Bit Division
8-Bit DivisionJust as binary multiplication can be
carried out as a series of add and shift operations, division can be carried out by a series of subtraction and shift operations.
To construct the divider, we will use a 9-bit dividend register and a 4-bit divisor register.
During the division process, instead of shifting the divisor to the right before each we will shift the dividend to the left.
Note that an extra bit is required on the left end of the dividend register so that a bit is not lost when the dividend is shifted left.
Instead of using a separate register to store the quotient, we will enter the quotient bit-by-bit into the right end of the dividend register as the dividend is shifted left.
Circuits for initially loading the dividend into the register will be added later.
8-Bit Division
8-Bit Division Initially, the dividend and divisor are entered as
follows:
Blue area shows that these four registers are for quotient bits.
Bits in red color show the dividend bits In this example subtraction cannot be carried out
without a negative result, so we will shift before we subtract.
X8 X7 X6 X5 X4 X3 X2 X1 X0
1 0 0 0 0 1 1 11 1 0 1Y3 Y2 Y1 Y0
8-Bit Division Instead of shifting the divisor one place to
the right, we will shift the dividend one place to the left:
Now 1101 is subtracted from 10000 and result is stored at X8 X7 X6 X5 X4 and at X0 the quotient 1 is stored
X8 X7 X6 X5 X4 X3 X2 X1 X0
1 0 0 0 0 1 1 1 01 1 0 1Y3 Y2 Y1 Y0
X8 X7 X6 X5 X4 X3 X2 X1 X0
0 0 0 1 1 1 1 1 11 1 0 1Y3 Y2 Y1 Y0
8-Bit Division Next, we shift the dividend one place to the left:
Subtraction is not possible because it would produce a negative result.
Shift the dividend to the left again, and the second quotient bit remains 0:
X8 X7 X6 X5 X4 X3 X2 X1 X0
0 0 1 1 1 1 1 1 01 1 0 1Y3 Y2 Y1 Y0
X8 X7 X6 X5 X4 X3 X2 X1 X0
0 1 1 1 1 1 1 0 01 1 0 1Y3 Y2 Y1 Y0
8-Bit Division Now 1101 is subtracted from 01111 and result is
stored at X8 X7 X6 X5 X4 and at X0 the quotient 1 is stored.
Next, we shift the dividend one place to the left:
Yellow shaded area is the remainder and blue shaded area is quotient or answer
X8 X7 X6 X5 X4 X3 X2 X1 X0
0 0 0 1 0 1 1 0 11 1 0 1Y3 Y2 Y1 Y0
X8 X7 X6 X5 X4 X3 X2 X1 X0
0 0 1 0 1 1 0 1 01 1 0 1Y3 Y2 Y1 Y0
Divider Overflow If the quotient would contain more bits than are
available for storing the quotient, we say that an overflow has occurred.
For the divider, we have previously considered, overflow would occur if the quotient is greater than 4 bits.
It is not actually necessary to carry out the division to determine if an overflow condition exists, because an initial comparison of the dividend and divisor will tell if the quotient will be too large.
For example, if we attempt to divide 135 by 7, the initial contents of the registers would be:
Divider OverflowBecause subtraction can be carried out with
a nonnegative result, we should subtract the divisor from the dividend and enter a quotient bit of 1 in the rightmost place in the dividend register.
However, we cannot do this because the rightmost place contains the least significant bit of the dividend, and entering a quotient bit here would destroy that dividend bit.
Therefore, the quotient would be too large to store in the 4 bits we have allocated for it, and we have detected an overflow condition.
Divider Overflow DetectionIf initially X8 X7 X6 X5 X4 ≥ Y3 Y2 Y1 Y0
i.e., if the left five bits of the dividend register exceed or equal the divisor,Then the quotient will be greater than 15 and an overflow occurs.
Operation of the Divider Circuit A shift signal (Sh) shifts the dividend one place to
the left on the next rising clock edge. Because the subtracter is a combinational circuit, it
computes X8 X7 X6 X5 X4 - Y3 Y2 Y1 Y0, and this difference appears at the subtracter output after a propagation delay.
A subtract signal (Su) will load the subtracter output into X8 X7 X6 X5 X4 and set the quotient bit (the rightmost bit in the dividend register) to 1 on the next rising clock edge.
To accomplish this, Su is connected to both the Ld input on the shift register and the data input on flip-flop X0.
8-Bit Division
Operation of the Divider Circuit If the divisor is greater than the five
leftmost dividend bits, the comparator (we see later on that how a comparator works) output is C=0; otherwise, C=1.
The control circuit generates the required sequence of shift and subtract signals.
Whenever C=0, subtraction cannot occur without a negative result, so a shift signal is generated.
Whenever C=1, a subtract signal is generated, and the quotient bit is set to one.
Operation of Divider Circuit When a start signal (St) occurs, the 8-bit dividend
and 4-bit divisor are loaded into the appropriate registers.
If C is 1, the quotient would require five or more bits. Because space is only provided for a 4-bit quotient,
this condition constitutes an overflow, so the divider is stopped, and the overflow indicator is set by the V output.
Normally, the initial value of C is 0, so a shift will occur first.
Then, if C=1, subtraction occurs. After the subtraction is completed, C will always be 0,
so the next active clock edge will produce a shift.
At S0 : ◦ If input is St (Start) = 0; remain at S0 (stop state)◦ if input St (Start) =1 then Ld (Load) = 1 which
loads the divisor and dividend into the registers. At S1 :
◦ If input is C = 0 then output is Sh (Shift) = 1 which indicates to shift the values in the dividend register once.
◦ If Input C = 1 then V = 1 which indicates overflow will occur therefore stop the division process.
At S2, S3 and S4 : ◦ If input is C = 0 then Sh=1◦ If Input C = 1 then Su (Subtracter) = 1 which indicates to
load the subtracter output into X8 X7 X6 X5 X4 and set the quotient bit (the rightmost bit in the dividend register) to 1 on the next rising clock edge and remain at the same state.
At S5 : ◦ If input C = 0 then no output is generated and divider stops
division process.◦ If Input C = 1 then Su (Subtracter) = 1 which indicates to
load the subtracter output into X8 X7 X6 X5 X4 and set the quotient bit to 1 and then stop the division process.
This process continues until four shifts have occurred.
Then, a final subtraction occurs if C=1, and no subtraction occurs if C=0.
No further shifting is required, and the control goes to the stop state.
For this example, we will assume that when the start signal (St) occurs, it will be 1 for one clock time, and, then, it will remain 0 until the control circuit is back stop state.
Divider SubtracterThe subtracter can be constructed
using five full subtracters, as shown in the figure on the next slide.
The borrow signal will propagate through the full subtracters before the subtracter output is transferred to the dividend register.
If the last borrow signal (b9) is 1, this means that the result is negative.
5 Bit Subtracter
8-Bit Divider Hence, if b9 is 1, the divisor (Y3Y2Y1Y0) is greater
than X8X7X6X5X4, and C = 0. Therefore, C=b9´, and a separate comparator
circuit is unnecessary. Normal operating conditions (no overflow) for this
divider, we can also show that C=d8’. ◦ At any subtraction step, because the divisor is only four
bits, d8 = 1 would allow a second subtraction without shifting.
◦ However, this can never occur because the quotient digit cannot be greater than 1.
◦ Therefore, if subtraction is possible, d8 will always be 0 after the subtraction, so d8 = 0 implies X8X7X6X5X4 is greater than Y3Y2Y1Y0 and C=d8´.
8-Bit Divider Bus mergers
and splitters do not require any actual hardware
They are just a symbolic way of showing bus connections.
8-Bit Divider The dividend is loaded in at the X register a MUX. The X register is a left-shift register with parallel load
capability On the rising clock edge, it is loaded when Ld = 1 and
shifted left when Sh = 1. Because the register must be loaded with the dividend when
Load = 1 and with the subtracter output when Su = 1, Load and Su are ORed together and connected to the Ld input.
The MUX selects the dividend (preceded by a 0) when Load 1.
When Load 0, it selects the bus merger output which consists of the subtracter output, X3X2X1, and a logic 1.
When Su = 1 and the clock rises, this MUX output is loaded into X.
The net result is that X8X7X6X5X4 gets the subtracter output, X3X2X1 is unchanged, and X0 is set to 1.
Binary Coded Decimal (BCD) A format for representing decimal numbers (integers) Each digit is represented by four bits, (a nibble). The 4 bits represent the numbers 0 to 9.
BCD Denary0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9
Unpacked and Packed BCDIn unpacked BCD each decimal digit
is represented by 8 bits (i.e. 1 byte)45 = 00000100 00000101
In packed BCD each decimal digit is represented by 4 bits (i.e. 1 nibble)
45 = 0100 0101
BCD AdditionEither packed or unpacked BCD numbers
can be summed. BCD addition follows the same rules
as binary addition.Any binary sum ≥ 10 results in invalid BCD number. If the addition produces a carry and/or
creates an invalid BCD number, an adjustment is required to correct the sum.
The correction method is to add 6 to the sum in any digit position that has caused an error.
Not 6 is to be always added with the binary number to get its BCD value.
6 is only for the decimal numbers from 10 to 19.
For 20 to 29, you will have to add 12 (1100).
For 30 to 39, you have to add 18 (10010) and so on.
BCD Addition Examples24 + 13 = 37
0010 0100 = 24 0001 0011 = 130011 0111 = 37
15 + 9 = 240001 0101 = 150000 1001 = 090001 1110 = 114 Invalid0000 0110 = 60010 0100 = 24
Why Add 6 in BCD?Suppose we have to add 9+9 = 18In binary addition
1001 (9) + 1001 (9) = 10010 (18)10But in BCD 18 = 0001 1000 (24)10 Subtracting decimal value of binary
from decimal value of BCD number = 24 – 18 = 6
Therefore if we add binary value of 6 in the answer of binary addition if the value ≥ 10 then we get the correct BCD value.
4 Bit BCD AdderTo implement a 4-bit BCD adder we
need two 4-bit full adders. One to add two 4-bit BCD numbers
and the other full adder to add 2’s complement of 1010 (which is 0110) to the result if Cn = 1
Also we need 2 AND gates and one OR gate to generate Cn.
BCD SUM = 0001 0011
Assignment 2 Find the BCD values for
1000 (8) + 0110 (6)1001 (9)+ 1001 (9)0101 (5) + 0100 (4) using the BCD logic gate diagram.
Why addition of 1111 + 1111 cannot be performed in BCD adder?
Logic circuit diagram for 8 bit BCD adder and how it works?
8-bit BCD Adder
B7A7 B6A6 B5A5 B4A4
BCD Subtraction 9’s COMPLEMENT THE 9’s COMPLEMENT OF A DECIMAL NUMBER IS FOUND
BY SUBTRACTING EACH DIGIT IN THE NUMBER FROM 9.
9’s COMPLEMENT of 28 = 99 –28 = 71
9’s COMPLEMENT of 562 = 999 –562 = 437
Decimal Number
9’s Complement
Decimal Number
9’s Complement
0 9-0 = 9 5 9-5 = 41 9-1 = 8 6 9-6 = 32 9-2 = 7 7 9-7 = 23 9-3 = 6 8 9-8 = 14 9-4 = 5 9 9-9 = 0
BCD SubtractionSUBTRACTION OF A SMALLER DECIMAL
NUMBER FROM A LARGER ONE CAN BE DONE BY 1. ADDING THE 9’s COMPLEMENT OF THE
SMALLER NUMBER 2. TO THE LARGER NUMBER AND 3. THEN ADDING THE CARRY TO THE RESULT
(END AROUND CARRY).WHEN SUBTRACTING A LARGER NUMBER
FROM A SMALLER ONE THERE IS NO CARRY AND THE RESULT IS IN 9’s COMPLEMENT FORM AND NEGATIVE.
BCD Subtraction Examples:
OF 21
OF 28
BCD Subtraction 9’s complement rule of subtraction for decimal number is
applied for BCD number also.RULES:1. ADD 9’s COMP. OF B TO A
2. IF RESULT > 9, CORRECT BY ADDING 0110
3. IF MOST SIGNIFICANT CARRY IS PRODUCED [i.e. =1] THEN
THE RESULT IS POSITIVE ANDTHE END AROUND CARRY MUST BE ADDED.
4. IF MOST SIGNIFICANT CARRY IS 0 [i.e. NO CARRY] THEN THE RESULT IS NEGATIVE AND WE GET THE 9’s COMP. OF THE RESULT.
BCD SubtractionExamples
+0100 = 49’s Complement of 4 is 5. Hence answer is -5
9’s complement of 8 =1
BCD SubtractionExamples
BCD SubtractionExamples
8-Bits BCD Subtracter
BCD to 7 Segment Display Decoder
a should glow for 0, 2, 3, 5, 6, 7, 8, 9 b should glow for 0, 1, 2, 3, 4, 7, 8, 9 c should glow for 0, 1, 3, 5, 6, 7, 8, 9 d should glow for 0, 2, 3, 5, 6, 8, 9 e should glow for 0, 2, 4, 6, 8 f should glow for 0,4, 5, 6, 8, 9 g should glow for 2, 3, 4, 5, 6, 8, 9
b3b2b1b0
a b c d e f g
0000 0 1 1 1 1 1 1 00001 1 0 1 1 0 0 0 00010 2 1 1 0 1 1 0 10011 3 1 1 1 1 0 0 10100 4 0 1 0 0 1 1 10101 5 1 0 1 1 0 1 10110 6 1 0 1 1 1 1 10111 7 1 1 1 0 0 0 01000 8 1 1 1 1 1 1 11001 9 1 1 1 1 0 1 1101010111100110111101111
a should glow for 0, 2, 3, 5, 6, 7, 8, 9 b should glow for 0, 1, 2, 3, 4, 7, 8, 9 c should glow for 0, 1, 3, 5, 6, 7, 8, 9 d should glow for 0, 2, 3, 5, 6, 8, 9 e should glow for 0, 2, 4, 6, 8 f should glow for 0,4, 5, 6, 8, 9 g should glow for 2, 3, 4, 5, 6, 8, 9
a
00 01 11 10
00 1 0 1 101 0 1 1 111 x x x x10 1 1 x x
b1b0
b3b2
b3b2b1b0 a0000 10001 00010 10011 10100 00101 10110 10111 11000 11001 1
130202 bbbbbba
b
00 01 11 10
00 1 1 1 101 1 0 1 011 x x x x10 1 1 x x
b1b0
b3b2
b3b2b1b0
0000000100100011010001010110011110001001
02020 bbbbbb
b1111100111
c
00 01 11 10
00 1 1 1 001 0 1 1 111 x x x x10 1 1 x x
b1b0
b3b2
b3b2b1b0
0000000100100011010001010110011110001001
231203 bbbbbbc
c1101011111
Assignment 2Find functions for a, b, c, d, e, f and g
for BCD to 7 segment decoder
ComparatorsThe basic function of a comparator is to
compare the magnitude of two binary quantities to determine the relationship of those quantities.
When we compare two numbers then there are three possible outputs.
Suppose A and B are two numbers then eitherA = BA > BA < B
Comparator An XOR gate can be used to compare the two
values. Let A and B two single bit binary numbers, then
if A = 1 and B =1 the output of XOR = 0if A = 0 and B =0 the output of XOR = 0if A = 0 and B =1 the output of XOR = 1if A = 1 and B =0 the output of XOR = 1
In other words whenever the two input values are equal the output is 0, andwhenever the two inputs are unequal the output is 1
XNOR
A B A=B A<B A>B0 0 11 1 10 1 11 0 1
Multibit Magnitude ComparatorTo determine if A is greater than or
less than B, we inspect the relative magnitudes of significant digits.
If the two digits are equal, we compare the next lower significant pair of digits.
The comparison continues until a pair of unequal digits is reached.
Multi Magnitude Comparator In order to compare two bit binary numbers additional
XOR gate are needed. The two LSBs of the two numbers are compared by XOR
gate 1. The two MSBs of the two numbers are compared by
XOR gate 2. The outputs of gate 1 and 2 are inverted and applied to
the input of an AND gate. When the two input bits for each XOR gate are equal
then the output of the XOR gates is 0, which is inverted to 1 by the NOT gates.
Input values of the AND gate are 1, thus the output is 1 when both the numbers are equal.
Otherwise the output will be 0, which indicates that the numbers are unequal.
74HC85 Comparator It has three cascading inputs: A<B, A=B, A>B.These inputs allow several comparators to be
cascaded for comparison of any number of bits greater than four.
To expand the comparator, the A<B, A=B and A>B outputs of the lower order comparator are connected to the corresponding cascading inputs of the next higher order comparator.
The lowest-order comparator must have HIGH on the A=B input and LOWs on the A<B and A>B.
74HC85 Comparator
74HC85 Cascading
EncodersAn encoder accepts an active level on one
of its inputs representing a digit, such as a decimal or octal digit, and converts it a coded output, such as a BCD or binary.
A simple binary encoder circuit can receive a single active input out of 2n input lines generate a binary code on n parallel output lines.
For example a 4 to 2 encoder takes in 4 bits and outputs 2 bits.
Common encoders are 4-to-2, 8-to-3, 16-to-4, 32-to-5 etc.
Types of Encoder There are two main types of digital encoder. The Binary
Encoder and the Priority Encoder. The Binary Encoder converts one of 2n inputs into an n-
bit output. Then a binary encoder has fewer output bits than the input code.
◦ Binary encoders are useful for compressing data and can be constructed from simple AND or OR gates.
◦ One of the main disadvantages of a standard binary encoder is that it would produce an error at its outputs if more than one input were active at the same time. To overcome this problem priority encoders were developed.
The Priority Encoder is another type of combinational circuit similar to a binary encoder, except that it generates an output code based on the highest prioritized input.
◦ Priority encoders are used extensively in digital and computer systems as microprocessor interrupt controllers where they detect the highest priority input.
Encoders Applications Keyboard Encoder Priority encoders can be used to reduce the number of wires
needed in a particular circuits or application that have multiple inputs.
For example, assume that a microcomputer needs to read the 104 keys of a standard QWERTY keyboard where only one key would be pressed either "HIGH" or "LOW" at any one time.
One way would be to connect all 104 wires from the keys directly to the computer but this would be impractical for a small home PC, but another better way would be to use a priority encoder.
The 104 individual buttons or keys could be encoded into a standard ASCII code of only 7-bits (0 to 127 decimal) to represent each key or character of the keyboard.
Keypad encoders such as the 74C923 20-key encoder are available to do just that.
Encoder Applications Positional Encoders Another more common application is in magnetic
positional control as used on ships navigation or for robotic arm positioning etc.
For example, the angular or rotary position of a compass is converted into a digital code by a 74LS148 8-to-3 line priority encoder and inputted to the systems computer to provide navigational data and an example of a simple 8 position to 3-bit output compass encoder is shown below.
Magnets and reed switches could be used at each compass point to indicate the needles angular position.
Encoder Applications
Decimal to BCD EncoderThis type of encoder has ten inputs –
one for each decimal digit.Four outputs correspond to BCD
code.This is a basic 10-line-to-4-line
encoder.A Decimal to BCD encoder can be
implemented by OR gates.
Decimal to BCD EncoderDec
A3 A2 A1 A0
0 0 0 0 01 0 0 0 12 0 0 1 03 0 0 1 14 0 1 0 05 0 1 0 16 0 1 1 07 0 1 1 18 1 0 0 09 1 0 0 1
1 A0
A1
A2
A3
LSB
MSB
23
456789
Priority Encoder One more Important application of encoder is Priority Encoder
used to detect interrupts in microprocessor applications. The microprocessor uses interrupts to allow peripheral devices
such as the disk drive, scanner, mouse, or printer etc, to communicate with it,
But the microprocessor can only "talk" to one peripheral device at a time.
The processor uses "Interrupt Requests" or "IRQ" signals to assign priority to the devices to ensure that the most important peripheral device is serviced first.
The order of importance of the devices will depend upon their connection to the priority encoder.
Because implementing such a system using priority encoders such as the standard 74LS148 priority encoder IC involves additional logic circuits, purpose built integrated circuits such as the 8259 Programmable Priority Interrupt Controller is available.
IRQ Number Typical Use Description
IRQ 0 System timer Internal System Timer.IRQ 1 Keyboard Keyboard Controller.
IRQ 3 COM2 & COM4 Second and Fourth Serial Port.
IRQ 4 COM1 & COM3 First and Third Serial Port.
IRQ 5 Sound Sound Card.IRQ 6 Floppy disk Floppy Disk Controller.IRQ 7 Parallel port Parallel Printer.
IRQ 12 Mouse PS/2 Mouse.IRQ 14 Primary IDE Primary Hard Disk Controller.
IRQ 15 Secondary IDE Secondary Hard Disk Controller.
4-2 Encoder
D0
Q1
Q0
D3D2D1
4-2 Priority EncoderThey are often used to control
interrupt requests by acting on the highest priority request.
It includes priority function. If 2 or more inputs are equal to 1 at
the same time, the input having the highest priority will take precedence.
4-2 Priority Encoder
4-2 Priority Encoder In addition to two outputs Y0, and Y1, the
truth table has a third output designated by V, which is a valid bit indicator that is set 1 when one or more inputs are equal to 1.
If all inputs are 0, there is no valid input and V is equal to 0.
X says don’t care condition. It means that suppose inputs D0 and D3 both
are 1 simultaneously then at the output 111 will indicate that the input is D3 only because when D3 input is 1 then values of D0, D1 and D2 have no effect on the output.
4-2 Priority Encoder
8-3 Line Encoder A low at any single input will produce the output binary code
corresponding to that input. For instance , a low at A3’ will produce O2 =0, O1=1 and O0 =1,
which is binary code for 3. Ao’ is not connected to the logic gates because the encoder
outputs always be normally at 0000 when none of the inputs is LOW
8-3 Line Encoder
EI = Input Enable, EO = Output Enable, GS = Group Signal
GS is used to indicate when any of the inputs is active. EO, EI and GS are used to cascade the encoders in case
of number of bits > 8.
Binary Decoders Binary Decoders have inputs of 2-bit, 3-bit or 4-
bit codes depending upon the number of data input lines.
A decoder that has a set of two or more bits will be defined as having an n-bit code, and therefore it will be possible to represent 2n possible values.
A decoder generally decodes a binary value into a non-binary one by setting exactly one of its n outputs to logic “1″.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean number) it activates one and only one of its 2n outputs based on that input with all other outputs deactivated.
1-2 Line DecoderAn inverter ( NOT-gate ) can be
classed as a 1-to-2 binary decoder.1-input and 2-outputsAn input A can produce two
outputs A and A as shown.
2-4 Binary Decoder
Enable DecodersSome binary decoders have an additional
input pin labeled “Enable” that controls the outputs from the device.
This extra input allows the decoders outputs to be turned “ON” or “OFF” as required.
These types of binary decoders are commonly used as “memory address decoders” in microprocessor memory applications.
2-4 Decoder with Enable
3-8 Line Decoder
3-8 Line Decoder
Fan-in and Fan-outFan-out: The fan-out is the number
of gates that are connected to the output of the driving gate.Fan-out leads to increased load on the driving gate, and therefore longer propagation delay
Fan-In: The fan-in is the number of inputs that are connected to a logic gate.
4-16 Binary Decoder
4-16 Binary DecoderInputs A, B, C are used to select which
output on either decoder will be at logic “1″ (HIGH) and input D is used with the enable input to select which encoder either the first or second will output the “1″.
However, there is a limit to the number of inputs that can be used for one particular decoder, because as n increases, the number of AND gates required to produce an output also becomes larger resulting in the fan-out of the gates used to drive them becoming large.
4-16 Binary Decoder This type of active-”HIGH” decoder can be implemented
using just Inverters, ( NOT Gates ) and AND gates. It is convenient to use an AND gate as the basic decoding
element for the output because it produces a “HIGH” or logic “1″ output only when all of its inputs are logic “1″.
But some binary decoders are constructed using NAND gates instead of AND gates for their decoded output, since NAND gates are cheaper to produce than AND’s as they require fewer transistors to implement within their design.
The use of NAND gates as the decoding element, results in an active-”LOW” output while the rest will be “HIGH”.
As a NAND gate produces the AND operation with an inverted output, the NAND decoder looks like this with its inverted truth table.
Memory Address Decoder Binary Decoders are most often used in more
complex digital systems to access a particular memory location based on an “address” produced by a computing device.
In modern microprocessor systems the amount of memory required can be quite high and is generally more than one single memory chip alone.
One method of overcoming this problem is to connect lots of individual memory chips together and to read the data on a common “Data Bus”.
In order to prevent the data being “read” from each memory chip at the same time, each memory chip is selected individually one at time and this process is known as Address Decoding.
Memory Address DecodingEach memory chip has an input
called Chip Select or CS which is used by the microprocessor to select the appropriate memory chip.
Commonly a logic “1″ on this chip select input selects the device and a logic “0″ on the input de-selects it.
So by selecting or de-selecting each chip one at a time, allows us to select the correct memory address device for a particular address location.
Memory Address DecodingThe advantage of address decoding is
that when we specify a particular memory address, the corresponding memory location exists ONLY in one of the chips.
The binary decoder requires only 3 address lines, (A0 to A2) to select each one of the 8 chips (the lower part of the address), while the remaining 7 address lines (A3 to A9) select the correct memory location on that chip (the upper part of the address).
Memory Address Decoding
Multiplexer In electronics, a multiplexer or mux is a device that
selects one of several analog or digital input signals and forwards the selected input into a single line.
A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output.
An electronic multiplexer can be considered as a multiple-input, single-output switch i.e. digitally controlled multi-position switch.
The digital code applied at the select inputs determines which data inputs will be switched to output.
A common example of multiplexing or sharing occurs when several peripheral devices share a single transmission line or bus to communicate with computer.
MultiplexerEach device in succession is
allocated a brief time to send and receive data. At any given time, one and only one device is using the line.
This is an example of time multiplexing since each device is given a specific time interval to use the line.
Multiplexer is also called data selector
4:1 Multiplexer
S1 S0
8:1 Multiplexer
DemultiplexerDemultiplexer receives many signals
on single line and then distribute them to their respective receiving devices.
In other words it is the reverse operation of multiplexing.
The demultiplexer also converts the serial data at the input to parallel data.
1:8 Demultiplexer
1:8 Demultiplexer
Combinational & Sequential Logic Digital electronics is classified into◦ combinational logic and ◦ sequential logic.
Combinational logic output depends on the inputs levels. In sequential logic the output not only depends upon the current
values of the inputs, but also upon preceding input values. In other words, a sequential circuit remembers some of the past
output values — it has memory. Sequential circuits are constructed using combinational logic and
memory element with outputs fed back into the combinational logic forming a feedback path or loop
Feedback Logic Let's consider the basic feedback logic circuit below,
which is a simple NOT gate whose output is connected to its input.
The effect is that output oscillates between HIGH and LOW (i.e. 1 and 0).
Oscillation frequency depends on gate delay and wire delay. Assuming a wire delay of 0 and a gate delay of 10ns, then
oscillation frequency would be (on time + off time = 20ns) 50Mhz.
Feedback Logic The basic idea of having the feedback is to store the
value or hold the value, but in the above circuit, output keeps toggling.
We can overcome this problem with the circuit below, which is basically cascading two inverters.
The equivalent circuit is the same as having a buffer with its output connected to its input.
If Q is 0 it will always be 0, if it is 1 it will always be 1.
Feedback LogicHow to get a new value into the memory
cell?Answer:1. selectively break feedback path2. load new value into cell
SR LatchProblem: We cannot load a new value in
two cascaded inverters feedback logic except by switching the load and remember on and off manually (as shown on the previous slide).
Solution: The solution is SR Latch.An SR (set-reset) latch can be built using
two NOR gates forming a feedback loop.The output of the SR latch depends on
current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change.
SR Latch
Invalid State:Q and Q’ cannot be same
Memory State:Value of S changed from 1 to 0 but Q is unchanged
SR Latch SR latch have two inputs, S and R. S is called set and R is called reset. Q' is Q complementary output, so it always holds the
opposite value of Q. Set State: When Q=1 Reset State: When Q’=1 S = 1input causes the latch to set state (Q=1 and
Q’=0) The S input must go back to 0 before R is changed to
1 to avoid both S=1 and invalid state (i.e. S=1 and R=1).
Initially S is set to 1 and R to 0 to bring the latch to the set state.
Next slides show the initialization of an SR latch
Initially, the inputs and states of the latch are unknown as indicated by voltage levels of S and R.
Voltages of S and R @1 are neither 1 nor 0 but in between. @2 S is set to 0 and R to 1. This resets the latch with Q first becomes 0 and in
response Q’ becomes 1.
1 2
Next when R becomes 0 (@3), the latch remains reset, storing the 0 value on Q.
When S becomes 1 with R is 0 (@4), the latch is set, with Q’ goes to 0 first and in response Q becomes 1.
1 2 3 4
The delays in the changes of Q and Q’ after an input changes are directly related to the delays of the two NOR gates.
When S returns to 0 (5), the latch remains set, storing the 1 value present on Q.
When R becomes 1 with S is 0 (6), the latch is reset, with Q changing to 0 and in response Q’ becomes 1.
1 2 3 4 5 6
When R returns to 0 (7), the latch remains reset. When S and R both become 1(8), both Q and Q’
become 0 which invalid state. When S and R simultaneously return to 0, both Q
and Q’ take on unknown values.
1 2 3 4 5 6 7 8 9
This form of indeterminate state behavior for the (S,R) sequence of inputs (1,1),(0,0) results from assuming simultaneous input changes and equal gate delays.
S=0 & R = 1 Assume Q = 1 and Q' = 0 as present state
◦ Suppose change in Q occurs first Q = (R + Q')' = (1 + 0)’= 0 Q' = (S + Q)' = (0 + 0)’=1
◦ Suppose change in Q’ occurs first Q' = (S + Q)' = (0 + 1)’=0 invalid states of Q and Q’ Q = (R + Q’)' = (1 + 0)’=0 according to the function table
Assume Q = 0 and Q' = 1 as present state ◦ Q = (R + Q')' = (1 + 1)’ = 0 ◦ Q' = (S + Q)' = (0 + 0)’ = 1
1
0
Assume Q=1, Q’=0
1
0 1
0
Assume Q=0, Q’=1 1
0
1
0
S=0 & R=1 ConclusionIf the present value of Q=1 and Q’=0
then change in output Q must occur first otherwise invalid state of Q and Q’ will occur.
If the present value of Q=0 and Q’=1 then it does not matter whether value of Q changes first or Q’ changes first.
Hence if S=0 then Q=0
S=0 & R = 0Assume Q = 1 and Q’ = 0 as present
state ◦ Q = (R + Q')' = (0 + 0)’ = 1 unchanged◦ Q’ = (S + Q)’ = (0 + 1)’ = 0 unchanged
Assume Q = 0 and Q' = 1 as present state◦ Q = (R + Q')' = (0 + 1)’= 0 unchanged ◦ Q' = (S + Q)' = (0 + 0)’ = 1 unchanged
1
0
Assume Q=1, Q’=0
0
0 0
1Assume Q=0, Q’=1
1
0
1
0
S=0 & R=0 ConclusionIn this case it does not matter
whether value of Q changes first or Q’ changes first in both the present states of Q and Q’.
Hence if S=0 then Q=0
S=1 & R = 0 Assume Q = 1 and Q' = 0 as present state
◦ Q = (R + Q')' = (0 + 0)’ = 1 unchanged ◦ Q' = (S + Q)' = (1 + 1)’ = 0 unchanged
Assume Q = 0 and Q' = 1 as present state ◦ Suppose change in Q’ occurs first
Q' = (S + Q)' = (1 + 0)’ = 0 changed Q = (R + Q')' = (0 + 0)’ = 1 changed
◦ Suppose change in Q occurs first Q = (R + Q')' = (0 + 1)’ = 0 invalid states of Q and Q’ Q' = (S + Q)' = (1 + 0)’ = 0 according to the function table
1
0
Assume Q=1, Q’=0
0
10
1
Assume Q=0, Q’=1 1
0
0
1
S=1 & R=0 ConclusionIf Q=1 and Q’=0 then it does not
matter whether Q changes first or Q’ changes first.
If Q=0 and Q’=1 then value of Q’ should change before Q otherwise value of Q will be equal to zero which against the truth table values.
Q =1 only when S=1
S=1 & R = 1No matter what state Q and Q' are in,
application of 1 at input of NOR gate always results in 0 at output of NOR gate, which results in both Q and Q' set to LOW (i.e. Q = Q').
LOW in both the outputs basically is wrong, so this case is invalid.
1
0
Assume Q=1, Q’=0
1
1 0
0Assume Q=0, Q’=1
1
0
0
0
SR Latch Using NAND Gate
SR Latch Using NAND GateAfter comparing the truth tables of
SR latches constructed using NAND gates and NOR gates it is clear that NAND gate SR latch gives the same output at opposite inputs values of S and R.
For example set state Q=1 and Q’=0 is achieved when S=0 rather than 1.
In NOR gate S=1 and R=1 were invalid states where as in NAND gate S=0 and R=0 are invalid states.
Asynchronous and Synchronous Sequential CircuitsAsynchronous
◦State changes are abrupt◦Become active the moment any input
changes◦E.g. SR Latch
• Synchronous◦State changes are controlled by a “Clock”◦Clock allows ordering of events◦Parts of the computer are made of
synchronous sequential circuit components
ClockA “clock” is a special circuit that
sends electrical pulses through a circuit
Clocks produce electrical waveforms such as the one shown below◦Each pulse has a precise width◦There is a precise interval between pulses
– known as clock cycle time
Gated or Clocked SR Flip Flop Clocked latch is also called flip flop. The control signal pulses act as an enable signal for
inputs S and R. The output of the NAND gates stay at logic 1 level as
long as C=0. When C=1 then the input values at S and R will affect
the SR latch. SR latch changes it state whenever the input value is
changed. Set State: S=1, R=0 and C=1 Reset State: S=0, R=1 and C=1 When C=0 changes to 0 the SR latch remains in its
current state. C=0
Gated SR Flip FlopWhen Clock is 0 then Output does not change even when the input value changes.If input value changes but the clock is 0 then output will not change.
Latch and Flip FlopAn input enable signal can be used
for sampling the input (like gated SR).The two types of the enable signals
are:◦Level Sensitive or ( LATCH)◦Edge Sensitive or (Flip-Flop)
Difference between latch and flip flop is that flip flop controlled by a clock pulse.
In flip flop when the clock pulse is high the value is stored and remains the same until next high pulse of the clock.
Level Sensitive Sequential CircuitThe circuit shown on the next slide is
a modification of the RS logic we have discussed in the previous slides.
When Enable is HIGH, it transfers input S and R to the sequential cell transparently, so this kind of sequential circuits are called transparent Latch.
This is called RS Latch memory element with active high Enable.
Edge SensitiveThe change at the output Q occurs at
the rising edge of the pulse only.If any change occurs in before or
after the rising edge will have no effect on the output
Edge Sensitive
Change occurs at start of clock pulse HIGH
D Latch The SR latch seen earlier contains ambiguous state
when both the inputs are 1 (or 0 in case of NAND gate). To eliminate this condition we can ensure that S and R
are never equal. This is done by connecting S and R together with an
inverter. D Latch is the same as the SR latch, with the only
difference that there is only one input, instead of two (R and S).
This input is called D or Data input. Delay flip-flop or delay latch is another name used. In real world only D latch is used instead of SR latch. D flip-flop is very frequently used for data storage
circuits
D-Flip Flop
D Q1 10 0
Master Slave D Flip FlopA master-slave D flip-flop is created by
connecting two gated D latches in series, and inverting the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.
The term pulse-triggered means that data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of the clock pulse.
Master-Slave D Flip Flop
Master Slave D Flip Flop For a positive-edge triggered master-slave D flip-
flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1).
This allows the "master" latch to store the input value when the clock signal transitions from low to high.
As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked".
Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal.
Master Slave D Flip Flop This allows the signal captured at the rising edge
of the clock by the now "locked" master latch to pass through the "slave" latch.
When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge.
An implementation of a master-slave D flip-flop that is triggered on the positive edge of the clock
By removing the leftmost inverter in the above circuit, a D-type flip flop that strobes on the falling edge of a clock signal can be obtained.
Switch Debounce Circuit Practical use of SR circuit is eliminate mechanical
switch “bounce”. Switch bounce occurs when the contacts of any
mechanically operated switch, push-button or keypad are operated and the internal switch contacts do not fully close cleanly, but bounce together first before closing (or opening) when the switch is pressed.
This gives rise to a series of individual pulses which can be as long as tens of milliseconds that an electronic system or circuit such as a digital counter may see as a series of logic pulses instead of one long single pulse and behave incorrectly.
.
Switch Debounce Circuit
Switch Debounce CircuitFor example, during this bounce period the
output voltage can fluctuate wildly and may register multiple input counts instead of one single count.
Then set-reset SR Flip-flops circuits can be used to eliminate this kind of problem
Commonly available IC’s are ◦ MAX6816, single input, ◦ MAX6817, dual input ◦ MAX6818 octal input
These chips contain the necessary flip-flop circuitry to provide clean interfacing of mechanical switches to digital systems.
JK Flip Flop The ambiguous state output in the SR latch was eliminated in the
D latch by joining the inputs with an inverter. But the D latch has a single input. JK latch is similar to SR latch in that it has 2 inputs J (S) and K (R). JK Flip-flop is named after its inventor, Jack Kilby. Applications Of Flip-Flops◦ Counters◦ Frequency Dividers◦ Shift Registers◦ Storage Registers
Jack Kilby Jack Kilby was an
American electrical engineer who took part, along with Robert Noyce, in the realization of the first integrated circuit while working at Texas Instruments (TI) in 1958.
He was awarded the Nobel Prize in physics in 2000.
Jack Kilby
Robert Noyce co-founder of Fairchild Semiconductors and Intel Corp.
JK Flip Flop
If J and K are 0 then next state value of Q will always be same as the present value of Q.If J = 0 but K = 1 then next state value of Q will always be 0
If J = 1 but K = 0 then next state value of Q will always be 1If J and K are 1 then next state value of Q will always be reverse of the present value of Q.
JK Flip Flop Extended Characteristic Table
JK Flip Flop Extended Characteristic Table
JK Flip Flop Excitation Table
JK Flip Flop The cross coupling of the Q and Q’ outputs to J and K
NAND gates allows the invalid condition of both the inputs equal to 1.
JK flip-flop allows the previously invalid condition of S = “1″ and R = “1″ state to be used to produce a “toggle action” as the two inputs are now interlocked.
Latch state means that whatever the stored/last output value of Q is, will remain the same as long as J=0 and K=0
Suppose initially input J=0 and K=1 and output Q=0 and Q’=1.
After that J=0 and K=0 and the output values at Q=0 and Q’=1 will remain the same as long as the values of J and K remain 0.
JK Flip Flop Toggle stage means that the current state of Q
becomes last state of Q’ i.e. Qn = Q’n-1 and Q’n = Qn-1 This changing of Q from 0 to and 1 will continue until
the clock is HIGH. It means the output of Q and Q’ will be
Q = 0 → 1 → 0 → 1 → 0 → 1 → 0 → 1 → 0 ……..Q’ = 1 → 0 → 1 → 0 → 1 → 0 → 1 → 0 → 1 ……..until the clock is HIGH.
This kind of toggling is called RACING. In the toggle state the speed of change from 1 to 0 and
0 1 to 1 depends on the propagation delay of the NAND gates.
Racing can be avoided by setting the Clock ON time less than the Propagation Delay
ClockQ
Racing
Clock ON timePropagation delay time
This not a very practical solution because the input values at J and K usually do not arrive as fast as less than 10 ns (10-20 ns is the usual propagation delay time for a NAND gate).
Negative or falling edge JK flip flop
Positive or rising edge JK flip flop
Master Slave Flip FlopAs we have seen that making clock
on time smaller than the propagation delay of the NAND gate is not a practical solution of racing.
The more practical solution is Master Slave Flip Flop.
J=K=0When clock = 0, the slave becomes
active and master is inactive. But since the S and R inputs have not
changed, the slave outputs will also remain unchanged.
Therefore outputs will not change if J = K =0.
J=0, K=1 Clock = 1: Master active, slave inactive. Outputs of the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and R =1. Clock = 0: Slave active, master inactive Outputs of the slave become Q = 0 and Q bar = 1. Again clock = 1: Master active, slave inactive.
Therefore even with the changed outputs Q = 0 and Q bar = 1 fed back to master, its outputs will Q1 = 0 and Q1 bar = 1.
That means S = 0 and R = 1. Hence with clock = 0 and slave becoming active the
outputs of slave will remain Q = 0 and Q bar = 1. Thus we get a stable output from the Master slave.
J=1, K=0Clock = 1: Master active, slave
inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and R =0.
Clock = 0: Slave active, master inactive Therefore outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1: then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0.
J=K=1 Clock = 1: Master active, slave inactive.
Outputs of master will toggle. So S and R also will be inverted.
Clock = 0: Slave active, master inactive. Outputs of slave will toggle.
These changed output are returned back to the master inputs.
But since clock = 0, the master is still inactive, it does not respond to these changed outputs.
This avoids the multiple toggling which leads to the race around condition.
The master slave flip flop will avoid the race around condition.
Level Triggered JK Flip Flop
Positive Edge Triggered JK Flip Flop
Negative Edge Triggered JK Flip Flop
JK Flip Flop Frequency DividerThe time period of the clock time can be
reduced by using two JK flip flops in the following manner
The values of J and K will always be 1 for toggling.
Assignment Explain in detail the application of
frequency division in digital electronics.
Counters Major application of flip flops is found in binary counters. The same configuration of the JK flip flop used for
frequency division is used for counter as well. A flip flop counter works as an up counter and down
counter simultaneously. Q is the output for up counter and Q’ is the output for
down counter. The counter will be 2N. Hence, for 4 bit counter range is 0-15, 5 bit counter
range is 0-31, 6 bit counter range is 0-63 and so on. Counter starts from 0 and after reaching to the
maximum value it becomes 0 again. This kind of counter is also called modulo counter
because it resets to 0 after reaching the maximum value.
3-Bit Asynchronous Counter
UP COUNTER DOWN COUNTERQ2 Q1 Q0 Dec Q’0 Q’1 Q’2 Dec0 0 0 0 1 1 1 70 0 1 1 1 1 0 60 1 0 2 1 0 1 50 1 1 3 1 0 0 41 0 0 4 0 1 1 31 0 1 5 0 1 0 21 1 0 6 0 0 1 11 1 1 7 0 0 0 0
3-Bit Asynchronous Counter
Up/Down CounterUp counter is the output of Q of a JK
flip flopDown counter is the output of Q’ of a
JK flip flop.What if a 0-15 counter is to be used
for counting only up to 7 or 10 or 11 and then become 0 again.
For this purpose we use a JK flip flop with PRESET (P or PST) and CLEAR (CLR) gates.
Up/Down Counter PST and CLR are called overriding inputs because irrespective
values of J, K and CLK◦ as long as PST=0, Q=1 and Q’=0, and◦ when CLR becomes 0, Q=0 and Q’=1.PST CLR Q0 1 11 0 01 1 JK toggles normally
0 0 Causes uncertain output, hence must not be used
To set the value of Q = 0 set CLR to 0To set the value of Q= 1 set PST to 0
Arbitrary CountingSuppose we use a 3-bit counter to count for
0 to 5 only i.e. 0,1,2,3,4 and 5.Now to count up to 5 only we use CLR to
reset the counter to 0 when 5 is reached.But assuming there is no delay ( or very
small delay) then the moment 5 is reached the CLR resets the counter before 5 is completed for 1 clock ON period (or cycle) and practically the counting is done up to 4 only.
Hence to count up to 5 we reset the counter to 0 when counter reaches to 6 instead of 5.
Counting up to 5 only
UP COUNTERA B C Dec0 0 0 00 0 1 10 1 0 20 1 1 31 0 0 41 0 1 51 1 0 61 1 1 7
Asynchronous Arbitrary Counter
1
1
C=0 B=1 A =1
Only @ 110 NAND is active and output 0
0 @ 110
Asynchronous Arbitrary CounterNow suppose counting starts from 2 and
stops at 6 i.e. 2,3,4,5,6.As we now to count up to 6 we have to
reset the counter at 7.Unlike previous example we will not reset
the counter to 0 but 010=2 this time.Since at the start time the flip flops can be
in any state, the count cycle may start from any value like 5 or 4 or 7 or any other value.
But after on complete cycle of counting the counting will always start from 2.
Asynchronous Arbitrary Counter
1
1
C=0 B=1 A =1
Only @ 110 NAND is active and output 0
0 @ 110
Flip Flop Propagation Delay Let Tp is the propagation time delay on 1 flip flop For example for 8 bits counter we need 8 flip flops. Hence Tp (total) = Tp (1 flip flop) x 8 The counter we have just studied in previous
slides is called Ripple Counter. Ripple counter fails to perform when the clock rate
is very high. Reason is that the clock input of the next stage flip
flop is the output Q of the previous flip flop and the propagation time of the previous flip flop is the limit of processing speed for each next stage flip flop.
The solution is Synchronous Counter.
Synchronous Counter
Q1 toggles only when in Q0 has become 1
Synchronous Counter Output of 1st flip flop toggles with the clock
pulses. The 2nd flip flop will output toggle only when J
and K become 1. For 2nd flip flop J and K become 1 after two clock
cycles because @ clock cycle 1 J and K are 0. For toggling we know that both J and K must be
1. At clock cycle 2 J and K of 2nd flip flop become 1. Hence at clock cycle 3 J and K are 1 and output
of the 2nd flip flop toggles
Registers A group of flip flops is called Register. Registers are used to store data and move data. A 4 bit register would have 4 flip flops. Gated D flip flops are used for registers because
D flip flop uses single input and each flip flop stores 1 bit of data.
WE : Write EnableWhen WE=1 then data is input
In D flip flop when the clock rising edge is detected the output Q becomes equal to D.
In other words when clock rising edge is detected the D flip flop stores the input data.
A shift register is able to shift the data it contains by one bit either to the left or to the right.
They are used to transform serial data to parallel, and parallel to serial data.
Generally, shift registers operate in one of four different ways:
1. Serial-in to Serial-out (SISO) - The data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control.
2. Serial-in to Parallel-out (SIPO) - The register is loaded with serial data, one bit at a time, with the stored data being available in parallel form.
3. Parallel-in to Serial-out (PISO) - The parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.
4. Parallel-in to Parallel-out (PIPO) - The parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.
Serial In Serial Out RegisterThis type of shift registers will delay
the input data by one clock cycle for each stage.
Four D flip-flops are used as a serial-in/serial-out shift register.
0 1 2 3
On each rising edge of the clock:Data Out Q3=D3=Q2Q2 D2=Q1Q1 D1=Q0Q0 D0=Data In
Lets input Data 1101 1st Data In Bit = 1 (LSB)
At 1st rising edge of the clock flip flops take the input in and the Q state of each flip flop will be
Q0 Q1 Q2 Q31 0 0 0
2nd Data In Bit = 0At 2nd rising edge of the clock flip flops take the input in and the Q state of each flip flop will be
Q0 Q1 Q2 Q30 1 0 0
3rd Data In Bit = 1At 3rd rising edge of the clock flip flops take the input in and the Q state of each flip flop will be
Q0 Q1 Q2 Q31 0 1 0
4th Data In Bit = 1At 4th rising edge of the clock flip flops take the input in and the Q state of each flip flop will be
Q0 Q1 Q2 Q31 1 0 1
Now all the data input bits have been stored in the register. Data will remain stored until enable is 0 (enable is not shown in the fig) To Read or output data Enable=1 and Data In = 0
Q0 Q1 Q2 Q30 1 1 0
Q0 Q1 Q2 Q30 0 1 1
Q0 Q1 Q2 Q30 0 0 1
Q0 Q1 Q2 Q30 0 0 0
Serial In Parallel Out RegisterThe process of shifting the input data
bits is same as SISO register.LSB is input first for the following
configuration. Reset make all the outputs = 0
Parallel In Parallel Out The operation is quite straight forward. At the rising edge of the clock Q1, Q2, Q3 and Q4
have values of A, B, C and D,
Parallel In Serial Out Registers It is the bit more complex of all the shift registers. A logic is needed to determine whether you are loading data
to the register or shifting data currently in the register.
Each input to each flip flop can either be data in or data shifted from the previous flip flop.
Shift/ Load is used for that.If shift/load is HIGH the data will be
shifted and data in is disabled because load is 0 which ends with input bits.
When shift/load is LOW then load is 1 and data is input to the flip flops.
Bidirectional Shift Register A bidirectional shift register is one in which the data
can be shifted either left or right. It can be implemented by using gating logic that
enables the transfer of a data bit from one stage to the next stage to the right or to the left, depending on the level of a control line.
A 4-bit bidirectional shift register is shown below.
A HIGH on the RIGHT/ LEFT control input allows data bits inside the register to be shifted to the right\
A LOW enables data bits inside the register to be shifted to the left.
When the RIGHT/LEFT control input is HIGH, gates G1 through G4 are enabled, and the state of the Q output of each flip-flop is passed through to the D input of the following flip-flop.
When a clock pulse occurs, the data bits are shifted one place to the right.
When the RIGHT/LEFT control input is LOW, gates G5 through G8 are enabled, and the Q output of each flip-flop is passed through to the D input of the preceding flip-flop.
When a clock pulse occurs, the data bits are then shifted one place to the left.
Shift Register CountersA shift register counter is basically a
shift register with the serial output connected back to the serial input to produce special sequences.
These devices are often classified as counters because they exhibit a specified sequence of states.
Two of the most common types of shift register counters are:◦Ring counter ◦ Johnson counter
Ring CounterA ring counter is a Shift Register (a cascade
connection of flip-flops) with the output of the last flip flop connected to the input of the first.
It is initialized such that only one of the flip flop output is 1 while the remainder is 0.
The 1 bit is circulated so the state repeats every n clock cycles if n flip-flops are used.
The "MOD" or "MODULUS" of a counter is the number of unique states.
The MOD of the n flip flop ring counter is n. It can be implemented using D-type flip-flops.
1 0 0
STATE MACHINE
State MachinesThere are many ways of modeling the
behavior of systems, and the use of state machines is one of the oldest and best known.
State machines allow us to think about the “state” of a system at a particular point in time and characterize the behavior of the system based on that state.
Assume that the flip-flop inputs are stable a sufficient time before and after the active clock edge so that setup and hold time requirements are met.
Change in the state of the sequential circuit will always occur in response to the active clock edge.
The circuit output may change at the time the flip-flops change state or at the time the input changes depending on the type of circuit.
Counter Design Using State MachineArbitrary or random sequence
counter may count 1, 4, 3, 5, 2, 6 in a loop fashion.
ABC1 0014 1003 0115 1012 0106 110
S0S1
S2S3
S4
S5
+ shows that this is next state The combinational logic circuit is such that if ABC = 001(1)
input then at output (A+B+C+) it will produce 100(4) (i.e. next number) or if 110(6) is input then output should be 001 (1).
COBMIN-ATIONAL
LOGIC
A
B
C
A+
B+
C+
D Q
D Q
D Q
Clock
In order to use K-map for simplification we will put values of ABC in sequence.
This help us to avoid any problems may occur in simplification process.
Combinational Logic Truth Table
A B C A+ B+ C+
000 x x x001 1 0 0010 1 1 0011 1 0 1100 0 1 1101 0 1 0110 0 0 1111 x x x
For A+ B’C’ B’C BC BC’
00 01 11 10A’ 0 x 1 1 1A 1 XA+ = A’
For B+ B’C’ B’C BC BC’
00 01 11 10A’ 0 x 1A 1 1 1 xB+ = A’C’ + AB’
For C+ B’C’ B’C BC BC’
00 01 11 10A’ 0 x 1A 1 1 x 1C+ = AC’ + BC
D B B’
D C C’
D A A’
COMBINATIONAL LOGIC
A+
B+
C+
JK Flip Flop Extended Characteristic Table
JK Flip Flop Excitation Table
Design the Same Counter using JK Flip Flop
In case of D flip flop the input of the D flip flop was same as the output of the combinational logic circuit.
But in case of JK flip flop we have two inputs J and K
Combinational Logic Truth TablePresent StateA B C
NextStateA+ B+
C+
JA KA JB KB JC KC
000 x x x x x x x x x001 1 0 0 1 x 0 x x 1010 1 1 0 1 x x 0 0 x011 1 0 1 1 x x 1 x 0100 0 1 1 x 1 1 x 1 x101 0 1 0 x 1 1 x x 1110 0 0 1 x 1 x 1 1 x111 x x x x x x x x x
For JA B’C’ B’C BC BC’
00 01 11 10A’ 0 x 1 1 1A 1 x x x xJA = B’+B = 1
For JB B’C’ B’C BC BC’
00 01 11 10A’ 0 x 0 x xA 1 1 1 x xJB = A
For JC B’C’ B’C BC BC’
00 01 11 10A’ 0 x x x 0A 1 1 x x 1JC = A
For KA B’C’ B’C BC BC’
00 01 11 10A’ 0 x x x xA 1 1 1 x 1KA = B’+B = 1
For KB B’C’ B’C BC BC’
00 01 11 10A’ 0 x x 1 0A 1 x x x 1KB = A + C
For KC B’C’ B’C BC BC’
00 01 11 10A’ 0 x 1 0 xA 1 x 1 x xKC = B’
J B K B’
J C K C’
J A K A’
COMBINATIONAL LOGIC
11
Clock
MEALY AND MOORE CIRCUITS
Two types of clocked sequential circuits will be considered:◦those in which the output depends only
on the present state of the flip-flops and
◦those in which the output depends on both the present state of the flip-flops and on the value of the circuit inputs.
If the output of a sequential circuit is a function of the present state only, the circuit is often referred to as a Moore machine.
Moore Machine = Describes the output at a certain independent of the input value
If the output is a function of both the present state and the input, the circuit is referred to as a Mealy machine.
Mealy Machine = Output depends on the input value as well.
Mealy Machine Let’s assume a Mealy state graph as shown below. ‘x’ is input and ‘z’ is output. A and B are state variables All the values are chosen arbitrarily.
S0
S1S2
X=0Z =0X=
1Z =0 X=
1Z =0
X=0Z =1
X=0,1Z =0,1
COBMIN-ATIONAL
LOGIC
A
B
A+
B+
D Q
D Q
Clock
x z
A=0B=0
A=0B=1
A=1B=0
Mealy State TablePresent State
Input Next State
Output
A B x A+ B+ zS0 0 0 0 0 0 0
0 0 1 0 1 0S1 0 1 0 1 0 1
0 1 1 0 1 0S2 1 0 0 0 0 0
1 0 1 0 0 11 1 x x x 01 1 x x x 0
For z B’x’ B’x Bx Bx’
00 01 11 10A’ 0 0 0 0 1A 1 0 1 0 0z = AB’x + A’Bx’
For output ‘z’ we do not use DON’T’ CARE ‘x’ because it means the output can be either 1 or 0.Output 1 for undefined state is not the desired output and called GLITCH.Thereforfore for undefined state we use ‘0’ instead of ‘x’
Moore Machine Let’s assume a Mealy state graph as shown below. ‘x’ is input and ‘z’ is output. A and B are state variables All the values are chosen arbitrarily.
S0/Z=0
S1/Z=0
S2/Z=1
X=0Z =0X=
1Z =0 X=
1Z =0
X=0Z =1
X=0,1Z =0,1
COBMIN-ATIONAL
LOGIC
A
B
A+
B+
D Q
D Q
Clock
x z
A=0B=0
A=0B=1
A=1B=0
Moore State TablePresent State
Input Next State
Output
A B x A+ B+ zS0 0 0 0 0 0 0
0 0 1 0 1 0S1 0 1 0 1 0 0
0 1 1 0 1 0S2 1 0 0 0 0 1
1 0 1 0 0 11 1 x x x 01 1 x x x 0
For z B’x’ B’x Bx Bx’
00 01 11 10A’ 0 0 0 0 0A 1 1 1 0 0z = AB’
Output z is zero for both values of x because output is not affected by the input values or output is independent of input values.
BITS PATTERN DETECTOR USING MEALY MACHINE
Mealy State Graph Example 1Suppose we want to detect bit
pattern 010 in a receiving stream of bits ‘x’.
So whenever bit pattern 010 occurs the output ‘z’ becomes 1 and then becomes 0 again to detect another bit pattern.
Suppose x = 1001101000 is received
Then z = 0000000100z becomes 1 after it detects the last
bit of the pattern and then change to 0 again.
What if we have again 1 after the last pattern detected.
For example x = 10011010100. If you allow the overlapping (i.e last 0 is
counted as part of previous pattern as well as next pattern) then we can say we have two patterns otherwise it is not considered as a next pattern.
In this example we allow overlapping detection, hence the output will be
x = 10011010100 z = 00000001010
State Graph Assume when the circuit will be switched on it will
be in S0 state
S0
S1S2
x / z = 1 /0; If input bit is 1 then stay in the present state0/0; no output
0/0
1/0
S0 – Reset state (00)S1 – is the state in which 0 has been received (01)S2 – is the state in which 01 has been received (10)
0/11/0
State Graph At S0, If the first bit is 0 then it can be starting bit of
bit pattern 010. But if the first bit is 1 then it cannot be starting bit of
bit pattern 010 so we remain in starting state S0 If consecutive bits after the first bit are also 1 then
we still stay in the state S0. We change the state only when the first 0 bit is
received. When 0 is received then it may be part of 010
pattern but we change the state to S1 to remember occurrence of 0
Since the output will occur only when the pattern 010 is received, at receiving first 0 no output will be generated.
At S1 if the received bit is 0 then we stay at S1 because we want 1 after 0 to detect 010 pattern.
At S1 if 1 is received then we move to S2 but output will still be 0.
At S2 if 0 is received then it means that we have received the pattern 010 and output is produced but next state will be again S1 because the received 0 may be part of another 010 sequence as we saw in bit pattern example before.
If 1 is received at S2 then we need to move to S0 to start process of detection again.
Mealy State Graph Example 2Now detect two patterns: 1001 and
010Overlapping is also allowed.
Clock
x z
Moore MachineAs an example of a Moore circuit, we
will analyze circuit consists of two D-flip flops(shown on the next slide).
Assume ◦ input X = 011. ◦ initial state of A = B = 0◦all state changes occur after the rising
edge of the clock.The X input is synchronized with the
clock so that it assumes its next value after each rising edge.
Moore Machine
State of A=1 and B = 0 occur only after the first rising edge of the clock
Moore MachineBecause Z is a function only of the present
state (in this case, Z = A ⊕ B) the output will only change when the state changes.
A = DA and B = DB First input bit (MSB) is X = 0, so DA = 1 and DB
= 0. The state will change to A = 1 and B = 0 after
the first rising clock edge.Second input bit is 1.So, DA = 0, DB = 1 and the state changes to A
= 0 and B = 1 after the second rising clock edge.
Moore MachineThird input bit is 1, which makes DA = DB
= 1, and the next rising edge causes A=1 and B=1.
The resulting output sequence is Z =110. Note that for the Moore circuit, the
output which results from application of a given input does not appear until after the active clock edge
Therefore, the output sequence is displaced in time with respect to the input sequence.
Mealy MachineAs an example of a Moore circuit, we
will analyze circuit consists of two JK-flip flops(shown on the next slide).
Assume ◦ input X = 10101. ◦ initial state of A = B = 0
In this example, the output depends on both the input (X) and the flip-flop states (A and B), so Z may change either when the input changes or when the flip-flops change state.
First input bit X=1.The output is Z=1 and JB =KA=1. After the falling edge of the first clock
pulse, B changes to 1 so Z changes to 0.
PROGRAMMABLE LOGIC DEVICES
Programmable Logic Devices An IC that contains large numbers of gates, flip-flops, etc. that can be
configured by the user to perform different functions is called a Programmable Logic Device (PLD).
PLD belongs to a larger group of programmable chips called Application Specific IC (ASIC).
PLDs can be used to prototype design that will be implemented for sale in regular Ics.
The internal logic gates and/or connections of PLDs can be changed/configured by a programming process.
One of the simplest programming technologies is to use fuses. In the original state of the device, all the fuses are intact. Programming the device involves blowing those fuses along the paths that
must be removed in order to obtain the particular configuration of the desired logic function.
PLDs are typically built with an array of AND gates (AND-array) and an array of OR gates (OR-array).
Problems of using standard ICs in logic design are that they require hundreds or thousands of these ICs, considerable amount of circuit board space, a great deal of time and cost in inserting, soldering, and testing.
There are three fundamental types of standard PLDs: ◦ Read Only Memory (ROM) or Programmable ROM (PROM) ◦ Programmable Array Logic (PAL)◦ Programmable Logic Array (PLA). ◦ Complex Programmable Logic Device (CPLD), ◦ Field Programmable Gate Array (FPGA).
In order to show the internal logic diagram for such technologies in a concise form, it is necessary to have special symbols for array logic.
Figure shows the conventional and array logic symbols for a multiple input AND and a multiple input OR gate.
Read Only Memory (ROM)ROM is made of a fixed array of AND
gates and a programmable array of OR gates.
Fixed AND array with 2N outputs implemented using a 2 x 2N decoder.
The output of the decoder are minterms.Programmable OR Array with M outputs
lines to form up to M sum of minterms.A program for a ROM or PROM is simply a
multiple-output truth table.
ROMThe input lines to the AND array are
hard-wired and the output lines to the OR array are programmable.
Each AND gate generates one of the possible AND products (i.e., minterms)
Example Consider that the following Boolean functions are to
be developed using ROM. F1 (A, B, C) = ( 0,1,2,5,7) and F2 (A, B, C) = (1,4,6). When a combinational circuit is developed by means
of a ROM, the functions must be expressed in the sum of minterms or by a truth table.
Since there are three input variables, a ROM containing a 3-to-8 line decoder is needed to implement fixed AND array.
In addition, since there are two output functions, the OR array must contain at least two OR gates.
That means, a 23 × 2 ROM or 8 × 2 ROM is to be employed to realize the above functions.
Programmable Logic Array (PLA)One way to design a combinational logic
circuit it to get gates and connect them with wires.
One disadvantage with this way of designing circuits is its lack of portability.
You can now get chips called PLA (programmable logic arrays) and "program" them to implement Boolean functions.
PLA is quite simple to learn, and produces nice neat circuits too.
Programmable Logic Array (PLA) is a programmable device used to implement combinational logic circuits.
The PLA has programmable connections for both AND and OR arrays.
So it is the most flexible type of PLD.This layout allows for a large number
of logic functions to be synthesized in the sum of products canonical forms.
Note that the use of the word "Programmable" does not indicate that all PLAs are field-programmable; in fact many are programmed during manufacture in the same manner as a ROM.
This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors.
PLAs that can be programmed after manufacture are called FPLA (Field-programmable logic array).
Firmware:
FIFO
LIFO
ROM
Flash Memory
SIMM
DIMM
