Combinational Logic

Digital Circuits 2

4.1 Introduction

Logic circuits for digital systems may be combinational or sequential.

A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.

Digital Circuits 3

4.2 Combinational Circuits

Logic circuits for digital system Sequential circuits

contain memory elements the outputs are a function of the current inputs and the

state of the memory elements the outputs also depend on past inputs

Digital Circuits 4

A combinational circuits 2

n possible combinations of input values

Specific functions Adders, subtractors, comparators, decoders, encoders,

and multiplexers MSI circuits or standard cells

CombinationalLogic Circuit

n inputvariables

m outputvariables

Digital Circuits 5

A straight-forward procedure

F2 = AB+AC+BCT1 = A+B+CT2 = ABCT3 = F2'T1F1 = T3+T2

Digital Circuits 6

F1 = T3+T2 = F2'T1+ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)

+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC

A full-adder F1: the sum

F2: the carry

Digital Circuits 7

The truth table

Digital Circuits 8

4-4 Design Procedure

The design procedure of combinational circuits State the problem (system spec.) determine the inputs and outputs the input and output variables are assigned symbols derive the truth table derive the simplified Boolean functions draw the logic diagram and verify the correctness

Digital Circuits 9

Functional description Boolean function HDL (Hardware description language)

Verilog HDL VHDL

Schematic entry Logic minimization

number of gates number of inputs to a gate propagation delay number of interconnection limitations of the driving capabilities

Digital Circuits 10

Code conversion example BCD to excess-3 code

The truth table

Digital Circuits 11

The maps

Digital Circuits 12

The simplified functions z = D'

y = CD +C'D' x = B'C + B'D+BC'D'

w = A+BC+BD Another implementation

z = D' y = CD +C'D' = CD + (C+D)'

x = B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)' w = A+BC+BD

Digital Circuits 13

The logic diagram

Digital Circuits 14

Full-Adder The arithmetic sum of three input bits three input bits

x, y: two significant bits z: the carry bit from the previous lower significant bit

Two output bits: C, S

Digital Circuits 15

Digital Circuits 16

S = x'y'z+x'yz'+ xy'z'+xyz C = xy + xz + yz

S = z (xy)= z'(xy'+x'y)+z(xy'+x'y)'

= z'xy'+z'x'y+z((x'+y)(x+y'))= xy'z'+x'yz'+xyz+x'y'z C = z(xy'+x'y)+xy = xy'z+x'yz+ xy

Digital Circuits 17

Binary adder

Digital Circuits 18

Binary subtractor A-B = A+(2’s complement of B) 4-bit Adder-subtractor

M=0, A+B; M=1, A+B’+1

Digital Circuits 19

4-8 Magnitude Comparator

The comparison of two numbers outputs: A>B, A=B, A<B

Design Approaches the truth table

22n

entries - too cumbersome for large n use inherent regularity of the problem

reduce design efforts reduce human errors

Digital Circuits 20

Algorithm -> logic A = A3A2A1A0 ; B = B3B2B1B0

A = B if A3 = B3, A2 = B2, A1 = B1 and A0 = B0

equality: xi = AiBi + Ai'Bi'

(A = B) = x3x2x1x0

(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

Implementation xi = (AiBi'+Ai'Bi)'

Digital Circuits 21Fig. 4.17Four-bit magnitude comparator.

Digital Circuits 22

Combinational logic implementation each output = a minterm use a decoder and an external OR gate to

implement any Boolean function of n input variables

Digital Circuits 23

Demultiplexers a decoder with an enable input receive information on a single line and transmits it

on one of 2n possible output lines

Fig. 4.19 Two-to-four-line decoder with enable input

Digital Circuits 24

4-12 HDL Models of Combinational Circuits

▓ Modeling Styles:

Digital Circuits 25

Gate-level Modeling

▓ The four-valued logic truth tables for the and, or, xor, and not primitives

Digital Circuits 26

Gate-level Modeling

Example:

output [0: 3] D;wire [7: 0] SUM;

1. The first statement declares an output vector D with four bits, 0 through 3.

2. The second declares a wire vector SUM with eight bits numbered 7 through 0.

Digital Circuits 27

HDL Example 4-1

■ Two-to-one-line decoder

Digital Circuits 28

HDL Example 4-2

■ Four-bit adder: bottom-up hierarchical description

Digital Circuits 29

HDL Example 4-2 (continued)

Digital Circuits 30

Three-State Gates

■ Statement:

gate name (output, input, control);

Fig. 4.31 Three-state gates

Digital Circuits 31

Three-State Gates

■ Examples of gate instantiation

Digital Circuits 32

Fig. 4.32 Two-to-one-line multiplexer with three-state buffers

Digital Circuits 33

Dataflow Modeling

■ Verilog HDL operators

Example:

assign Y = (A & S) | (B & ~S)

Digital Circuits 34

HDL Example 4.3

Dataflow description of a 2-to-4-line decoder

Digital Circuits 35

HDL Example 4-4

Dataflow description of 4-bit adder

Digital Circuits 36

HDL Example 4-5

Dataflow description of 4-bit magnitude comparator

Digital Circuits 37

HDL Example 4-6

Dataflow description of a 2-to-1-line multiplexer

Conditional operator (?:)

Condition ? True-expression : false-expression

Example: continuous assignment

assign OUT = select ? A : B

Digital Circuits 38

Behavioral Modeling

if statement:if (select) OUT = A;

Behavioral description of a 2-to-1-line multiplexer

HDL Example 4-7

Digital Circuits 39

HDL Example 4-8

Behavioral description of a 4-to-1-line multiplexer

Digital Circuits 40

Writing a Simple Test Bench

initial block

Three-bit truth table

Digital Circuits 41

Writing a Simple Test Bench

Interaction between stimulus and design modules

Digital Circuits 42

Writing a Simple Test Bench

Stimulus module

System tasks for display

Digital Circuits 43

Syntax for $dispaly, $write, and $monitor:

Example:

Example:

Digital Circuits 44

HDL Example 4-9

Stimulus module

Digital Circuits 45

HDL Example 4-9 (Continued)

Digital Circuits 46

HDL Example 4-10

Gate-level description of a full adder

Digital Circuits 47

HDL Example 4-10 (Continued)