101047960 Combinational Logic Circuits PPT
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Transcript of 101047960 Combinational Logic Circuits PPT
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A.SANYASI RAOAssoc. Prof. & HoDDept. of ECE
Balaji Institute of Engineering & Sciences
Narsampet, Warangal
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What is a Combinational circuit?
At instant, the output of the logic circuit depends on
present inputs.
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Design procedure:
1. Identify the number of inputs and outputs required for
the design of the circuit.
2. Derive the truth table.3. Write the expression for the output either in SOP or POS
form.
4. Simplify the expression for the output.
5. Draw the logic circuit for the simplified expression.
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ADDERS
Logic circuit which performs the addition of binary numbers
Adders of two types:
1. Half Adder (H.A)
2. Full Adder (F.A)
Half Adder
It is a combinational logiccircuit which performs
addition of two binary
bits.
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A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1ABC
BABAS
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Full Adder
It is a combinational logic circuit which performs addition
of three binary inputs.
ABBAC
CCABBABAC
ABCCABCBABCAC
CBA
CBACBA
BCCBACBCBA
ABCCBACBACBAS
in
ininin
ininininout
in
inin
inininin
inininin
)(
)()(
)()(
)()(
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Realizing Full Adder with two Half Adders and one OR gate
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SUBTRACTORS
Logic circuit which performs subtraction of binary numbers.
Subtractors are of two types:
1. Half Subtractor (H.S)
2. Full Subtractor (F.S)
Half Subtractor
Half
Subtra
ctor
A
B
D
BOUT
A B Difference(D) Borrow(B0)
0 0 0 0
0 1 1 11 0 1 0
1 1 0 0
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BAB
BABAD
0
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Full SubtractorCombinational circuit which performs subtraction on three
binary digits.
Half
Subtra
ctor
A
Bin
D
BOUT
B
A B Bin D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1BABAB
BBBAABBAB
ABBBBABBABBAB
BBA
BBABBA
BBBBABBBBA
ABCBBABBABBAD
in
ininin
ininininout
in
inin
ininin
in
inininin
)(
)()(
)()(
)()(
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Half
Subtractor
Half
Subtractor
A
B
D
Bin
Bout
Realizing Full Subtractor using two Half Subtractors & one OR gate
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4-Bit Binary Parallel Adder
Each stage in the parallel adder depends on the previous
stage carry.
Delay time is additive.
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1s Complement Subtractor
It requires two stages of addition. When the end carry is
1, it has to be added with the LSB adder. If the end carry is
zero, single stage of addition produces the result but the
answer is negative.
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2s Complement Adder/Subtractor
Adder if M=0
Subtractor if M=1
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When the control input, M is 0 the output of XOR
gates are B3B2B1B0 and the circuit functions as a 2s
complement adder.
When the control input is 1 the output of XOR
gates are B3 B2
B1 B0
which is the 1s complement of the
subtrahend. Since the control input is 1, the binary 1 is
added with the LSB added with B3
B2
B1
B0
which
produces 2s complement of the subtrahend. Therefore
the circuit behaves as an 2s complement subtractor.
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BCD Adder
The BCD adder requires two stages of addition when the result is greater
than 9. the result will be greater than 9, if C4 = 1 or S3S2 = 1 or S3S1 = 1. Therefore
the logic expression for these conditions are Y= C4 + S3S2 + S3S1 . if Y=1, binary 6
must be added with S3S2 S1S0 which is performed by the lower stage adders.
A0 B0A1 B1A2 B2A3 B3
H.AF.A F.A F.A
F.A H.A
COUT S3 S2 S1 S0
C4
S2S3 S1
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Carry Look Ahead Adder
The parallel adder is ripple carry type in which the carryoutput of each full adder stage is connected to the carry input of the
next higher-order stage . Therefore, the sum and carry occurs; this
leads to a time delay in the addition process. This delay is known as
propagation delay.
One method of speeding up this process by eliminating inter
stage carry delay is called look ahead carry addition.
The Carry Look Ahead Adder is able to generate carriesbefore the sum is produced using the propagate and generate logic
to make addition much faster.
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It uses two functions: Carry Generate & Carry Propagate.
Consider full adder circuit. Here we define the above two functions
Ai
Bi
Ci
Pi
Gi
Si
Ci+1
iiii
iii
iii
iii
CPGC
CPS
aswrittenbecancarryandsumoutputThe
BAGBAP
1
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Gi is called a carry generate and it produces on
carry when both Ai and Bi are 1, regardless of the input
carry. Pi is called a carry propagate because it is the term
associated with the propagation of the carry from Ci to Ci+1
C1
= G0
+ P0.C
0
C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0C
3= G
2+ P
2.G
1+ P
2.P
1.G
0+ P
2.P
1.P
0.C
0
C4
= G3
+ P3.G
2+ P
3.P
2.G
1+ P
3P
2.P
1.G
0+ P
3P
2.P
1.P
0.C
0
Si = Ai Bi Ci = Pi Ci
Gi= A
i.B
iPi = (A
i B
i)
Since all carries' are dependent on C0 , they can be
generated simultaneously and the addition process becomes faster.
The hardware required is more. Hence the carry-look ahead adder is
expensive compared to parallel adder.
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A0B0
A1
B1
A2B2
A3
B3
P1
P2
P3
S0
S1
S2
S3
C4
C0
G3
G2
P3
P2
G1
P1
G0
P0P0
C1
C2
C3
C4
C0
CARRY
LOOK
AHEAD
GENERATOR
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COMPARATORS
A comparator is a logic circuit use to compare the magnitudes
of two binary numbers. It provide an output that is active when thetwo numbers are equal, or additionally provide outputs that signify
which of the numbers is greater when equality does not hold.
The XNOR gate (coincide gate) is a basic comparator, because
its output is a 1 only if its two input bits are equal.
Two binary numbers are equal, if and only if all their
corresponding bits coincide. For instance, two 4-bit binary numbers
A3A2A1A0 and B3B2B1B0 are equal. To implement this logic
))()()(( 00112233 BABABABAEquality
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2-bit Magnitude Comparator
The logic for a 2-bit magnitude comparator:
1. If A1 = 1 and B1 = 0, then A > B or
2. If A1 and B1 coincide and A0 = 1 and B1 = 0, then A > B. So
the logic for A > B is
00111 )(: 1 BABABAGBA
1. If A1 = 0 and B1 = 1, then A < B or
2. If AJ1 and B1 coincide and A0 = 0 and B0 = 1, then A < B.So the logic for A < B is
00111 )(: 1 BABABALBA
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If A1 and B1 coincide and if A0 and B0 coincide then A = B.
So the logic for A = B is
))((:0011
BABAEBA
A1
A1
B1
A0
B0
B1
A0
B0
A0
A1
B0
B1
A > B
A = B
A < B
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4 - B i t M a g n i t u d e C o m p a r a t o r
The logic for a 4-bit magnitude comparator:
1. If A3 = 1 and B3 = 0, then A > B or
2. If A3 and B3 coincide, and if A2 = 1 and B2 = 0, then A > B or
3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=1
and B2 = 0, then A > B or4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1
and B1 coincide, A0=1 and B1 = 0, then A > B or
So the logic for A > B is
00112233112233
22333
))()(())((
)(:3
BABABABABABABA
BABABAGBA
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The logic for A < B is:
1. If A3 = 0 and B3 = 1, then A < B or
2. If A3 and B3 coincide, and if A2 = 0 and B2 = 1, then A < B or3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=0
and B2 = 1, then A < B or
4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1
and B1 coincide, A0=0 and B1 = 1, then A < B orSo the logic for A < B is
00112233112233
22
333
))()(())((
)(:3
BABABABABABABA
BABABALBA
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2-Bit Binary Multiplier
A1
A0
B1 B0
A1 B0 A0 B0
A1 B1 A0 B1
P4
P3
P2
P1
A0
A1
B0
B1
B1
B0
P4 P3 P2 P0
H. A H. A
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MULTIPLEXERS
A Multiplexer (MUX) or data selector is a logic circuit that accepts several data
inputs and allows only one of them at a time to get through to the output.
The routing of the desired data input to the output is controlled by SELECT lines.
A MUX selects 1-out-of-N input data sources and transmits the selected data to a
single output channel. This is called Multiplexing.
MUX is also known as Many to One device.
2n
X n
MUX
2ni/p s
o/p
n select lines
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4 X 1 MUX
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
301201101001ISSISSISSISSY
I0
I3
S0
S1
Y
I1
I2
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Applications of Multiplexers
1. Data selection
2. Data routing
3. Operation sequencing
4. Waveform generation
5. Parallel to serial conversion
6. Logic function generation
L i F ti G t
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Logic Function Generator
A multiplexer can be used in place of logic gates to
implement a logic expression.
It can generate any Boolean algebraic function of a set ofinput variables.
A single IC can perform a function.
It is very easy to change the logic function implemented, if
and when redesign of a system becomes necessary.
Multiplexers can be used to implement a logic function
directly from the function table without the need for
simplification. The select inputs of the multiplexer are used
as the function variables. The inputs of the multiplexer are
connected to logic 1 and 0 to represent the missing and
available terms.
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Ex: Implementation of F(A,B,C) = m(1,3,5,6) using 8 : 1 MUX
0
1
2
3
4
5
6
7
1 0
S2 S1 S0
A B C
8 : 1
MUXY
E Implementation of F(A B C) (1 3 5 6) i 8 1 MUX
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Ex: Implementation of F(A,B,C) = m(1,3,5,6) using 8 : 1 MUX
Step 1: Select the MSB variable as input and the remaining as
selector lines variables to the MUX. If the function has n
variables, then the size of the required MUX is 2n-1
to
1.
Step 2: Draw the truth table for the given function.
Step 3: Complete the function table.a) if both the minterms are circled, apply 1 to the
corresponding MUX input.
b) if both are not circled, apply 0 to the corresponding
MUX input.c) if the top is circled and bottom is not circled, apply A1
to the corresponding MUX input.
d) if the top is not circled and bottom is circled, apply A
to the corresponding MUX input.
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I0
I1
I2
I3 S1 S0
B C
4 : 1
MUX Y
0
1
A
A1
A B C F0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
I0 I1 I2 I3
0 1 2 34 5 6 7
A1
A
0 1 A A1
DEMULTIPLEXER
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DEMULTIPLEXER
1 X 2n
DEMUX
2n
o/p si/p
n select lines
Demultiplexer, DEMUX does the reverse
operation of a MUX. It receives the message over
one input line and directs the message to of the many
output lines. Hence it known as One to Many device.
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S1 S0 D Y0 Y1 Y2 Y3
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1
DSSY
DSSY
DSSY
DSSY
013
012
011
010
Y0
Y1
Y2
Y3
S0 S1
D AND
AND
AND
AND