Chapter 2 – Combinational Logic CircuitsLogic Circuits

23
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Logic Circuits Part 3 – Additional Gates and Circuits HOANG Trang Reference: © 2008 Pearson Education Inc Reference: © 2008 Pearson Education, Inc.

Transcript of Chapter 2 – Combinational Logic CircuitsLogic Circuits

Page 1: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Computer Engineering 1 (ECE290)

Chapter 2 – Combinational Logic CircuitsLogic Circuits

Part 3 – Additional Gates and Circuits

HOANG Trang

Reference: © 2008 Pearson Education IncReference: © 2008 Pearson Education, Inc.

Page 2: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Overview Part 1 – Gate Circuits and Boolean Equations

• Binary Logic and GatesBinary Logic and Gates• Boolean Algebra• Standard Forms

Part 2 Circuit Optimization Part 2 – Circuit Optimization• Two-Level Optimization• K-map

M M i l ti• Map Manipulation

Part 3 – Additional Gates and Circuits• Other Gate Types• Exclusive-OR Operator and Gates• High-Impedance Outputs

Hoang Trang Reference: Chapter 2 - Part 3 2

Page 3: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Other Gate Types

Why?• Implementation feasibility and low cost• Power in implementing Boolean functions• Convenient conceptual representation• Convenient conceptual representation

Gate classifications• Primitive gate: a gate that can be described using a• Primitive gate: a gate that can be described using a

single primitive operation type (AND or OR) plus an optional inversion(s). AND, OR, NOT

• Complex gate - a gate that requires more than one primitive operation type for its description

P i iti t ill b d fi t

Hoang Trang Reference: Chapter 2 - Part 3 3

Primitive gates will be covered first

Page 4: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Buffer

A buffer is a gate with the function F = X

X F

In terms of Boolean function, a buffer is the same as a connection! => Why use it?

• A buffer: an electronic amplifier used to + improve circuit voltage levels

Hoang Trang Reference: Chapter 2 - Part 3 4

+ increase the speed of circuit operation.

Page 5: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NAND Gate

The basic NAND gate has the following symbol, ill t t d f th i tillustrated for three inputs:• AND-Invert (NAND)

XYZ

ZYX)Z,Y,X(F

NAND represents NOT AND, i. e., the AND function with a NOT applied The symbol

Z

function with a NOT applied. The symbol shown is an AND-Invert. The small circle (“bubble”) represents the invert function.

Hoang Trang Reference: Chapter 2 - Part 3 5

( ) p

Page 6: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NAND Gates (continued)

Applying DeMorgan's Law gives Invert-OR (NAND)XYZ

ZYX)Z,Y,X(F

This NAND symbol is called Invert-OR, since inputs are inverted and then ORed together.

AND-Invert and Invert-OR both represent the NAND gate. Having both makes visualization of circuit function easiercircuit function easier.

A NAND gate with one input degenerates to an inverter.

Hoang Trang Reference: Chapter 2 - Part 3 6

Page 7: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NAND Gates (continued)

The NAND gate is the natural implementation for CMOS t h l i t f hi d dCMOS technology in terms of chip area and speed.

The NAND gate is a universal gate (Universal gate - a gate type that can implement any Boolean function)gate type that can implement any Boolean function)

NAND usually does not have a operation symbol defined since• the NAND operation is not associative, and• we have difficulty dealing with non-associative

mathematics!mathematics!Recall: associative: X+(Y+Z)=(X+Y)+Z

X(YZ) = (XY)Z

Hoang Trang Reference: Chapter 2 - Part 3 7

( ) ( )

Page 8: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NOR Gate

The basic NOR gate has the following symbol, ill t t d f th i tillustrated for three inputs:• OR-Invert (NOR)

XYZ

ZYX)Z,Y,X(F +

NOR represents NOT - OR, i. e., the OR function with a NOT applied The symbolfunction with a NOT applied. The symbol shown is an OR-Invert. The small circle (“bubble”) represents the invert function.

Hoang Trang Reference: Chapter 2 - Part 3 8

( ) p

Page 9: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NOR Gate (continued)

Applying DeMorgan's Law gives Invert-AND (NOR)(NOR)

XYZ

This NOR symbol is called Invert-AND, since inputs are inverted and then ANDed together

Z

inputs are inverted and then ANDed together. OR-Invert and Invert-AND both represent the

NOR gate. Having both makes visualization ofNOR gate. Having both makes visualization of circuit function easier.

A NOR gate with one input degenerates to an

Hoang Trang Reference: Chapter 2 - Part 3 9

A NOR gate with one input degenerates to an inverter.

Page 10: Chapter 2 – Combinational Logic CircuitsLogic Circuits

NOR Gate (continued)

The NOR gate is a natural implementation for t h l i th th CMOS i t fsome technologies other than CMOS in terms of

chip area and speed. The NOR gate is a universal gate The NOR gate is a universal gate NOR usually does not have a defined operation

symbol sincesymbol since• the NOR operation is not associative, and• we have difficulty dealing with non-associativewe have difficulty dealing with non associative

mathematics!

Hoang Trang Reference: Chapter 2 - Part 3 10

Page 11: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Exclusive OR/ Exclusive NOR

The eXclusive OR (XOR) function is an important B l f ti d t i l i l i i itBoolean function used extensively in logic circuits.

The XOR may be:i l t d di tl l t i i it (t l• implemented directly as an electronic circuit (truly a gate) or

• implemented by interconnecting other gate types (used p y g g yp (as a convenient representation)

The eXclusive NOR function is the complement of the XOR function

By our definition, XOR and XNOR gates are

Hoang Trang Reference: Chapter 2 - Part 3 11

complex gates.

Page 12: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Exclusive OR/ Exclusive NOR

XOR and XNORs gate could be used for:Add / b / l i li• Adders/subtractors/multipliers

• Counters/incrementers/decrementers• Parity generators/checkers• Parity generators/checkers

Definitions• The XOR: YXYXYX • The XOR: • The XNOR):

YXYXYX

YXYXYX

Strictly speaking, XOR and XNOR gates do no exist for more that two inputs. Instead, they are

Hoang Trang Reference: Chapter 2 - Part 3 12

replaced by odd and even functions.

Page 13: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Truth Tables for XOR/XNOR

Operator Rules: XOR XNORX Y XY

0 0 0

X Y

0 0 1or XY

(XY)

0 0 00 1 11 0 1

0 0 10 1 01 0 0

The XOR function means:X OR Y but NOT BOTH

1 1 0 1 1 1

X OR Y, but NOT BOTH Why? XNOR function is the equivalence function,

denoted by the operator“”?

Hoang Trang Reference: Chapter 2 - Part 3 13

y p

Page 14: Chapter 2 – Combinational Logic CircuitsLogic Circuits

XOR/XNOR (Continued)

The XOR function can be extended to 3 or more variables For more than 2 variables it is called an oddvariables. For more than 2 variables, it is called an odd function or modulo 2 sum (Mod 2 sum):

ZYXZYXZYXZYXZYX The complement of the odd function is the even

function. Th XOR id titi The XOR identities:

X1XX0X 1XX0XX 1XX0XX

XYYX ZYX)ZY(XZ)YX(

Hoang Trang Reference: Chapter 2 - Part 3 14

Page 15: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Symbols For XOR and XNOR

XOR symbol:

XNOR symbol:

Shaped symbols exist only for two inputs

Hoang Trang Reference: Chapter 2 - Part 3 15

Page 16: Chapter 2 – Combinational Logic CircuitsLogic Circuits

XOR Implementations

The simple SOP implementation uses the f ll i t tfollowing structure: X

X Y

Y

X Y

A NAND only implementation is:X

X Y

Hoang Trang Reference: Chapter 2 - Part 3 16

Y

Page 17: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Odd and Even Functions

The odd and even functions on a K-map form “ h k b d” tt“checkerboard” patterns.

The 1s of an odd function correspond to minterms having an index with an odd number of 1shaving an index with an odd number of 1s.

The 1s of an even function correspond to minterms having an index with an even number of 1shaving an index with an even number of 1s.

Implementation of odd and even functions for greater than four variables as a two-level circuit isgreater than four variables as a two level circuit is difficult, so we use “trees” made up of : • 2-input XOR or XNORs

Hoang Trang Reference: Chapter 2 - Part 3 17

p• 3- or 4-input odd or even functions

Page 18: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Example: Odd Function Implementation

Design a 3-input odd function F = X Y Zith 2 i t XOR t

+ +with 2-input XOR gates

Factoring, F = (X Y) ZTh i it

+ + The circuit:

XY

ZF

Z

Hoang Trang Reference: Chapter 2 - Part 3 18

Page 19: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Example: Even Function Implementation

Design a 4-input odd function F = W X Y Zith 2 i t XOR d XNOR t

+ + +with 2-input XOR and XNOR gates

Factoring F = (W X) (Y Z)Th i it

+ + + The circuit:

WX

FYZ

Hoang Trang Reference: Chapter 2 - Part 3 19

Page 20: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Parity Generators and Checkers a parity bit added to n-bit code to produce an n + 1 bit

code:• Add odd parity bit to generate code words with even parity• Add even parity bit to generate code words with odd parity• Use odd parity circuit to check code words with even parity• Use even parity circuit to check code words with odd parity

Example: n = 3. Generate evenparity code words of length four

XYp y g

with odd parity generator: Check even parity code words of

length four with odd parity checker:

YZ P

XYlength four with odd parity checker:

Operation: (X,Y,Z) = (0,0,1) gives(X,Y,Z,P) = (0,0,1,1) and E = 0.If Y changes from 0 to 1 between

Y

ZE

P

Hoang Trang Reference: Chapter 2 - Part 3 20

If Y changes from 0 to 1 betweengenerator and checker, then E = 1 indicates an error.

P

Page 21: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Hi-Impedance Outputs Logic gates introduced

• have 1 and 0 output values,have 1 and 0 output values, • cannot have their outputs connected together, and• transmit signals on connections in only one direction.

Three-state logic adds a third logic value, Hi-Impedance (Hi-Z), giving three states: 0, 1, and Hi-Z on the outputs.

The presence of a Hi-Z state makes a gate output i i iffas described above behave quite differently:

• “1 and 0” become “1, 0, and Hi-Z”“ t” b “ ” d

Hoang Trang Reference: Chapter 2 - Part 3 21

• “cannot” becomes “can,” and• “only one” becomes “two”

Page 22: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Hi-Z Outputs (continued) What is a Hi-Z value?

• The Hi-Z value behaves as an open circuitThe Hi Z value behaves as an open circuit(a switch between the internal circuitry and the output has

been opened)

Hi-Z may appear on the output of any gate, but restrict gates to:• a 3-state buffer, or• Optional: a transmission gate

each of which has + one data input

Hoang Trang Reference: Chapter 2 - Part 3 22

+ one control input.

Page 23: Chapter 2 – Combinational Logic CircuitsLogic Circuits

Hi-Z: the 3-State Buffer

For the symbol and Symboltruth table, IN is the data input, and EN, the

IN

EN

OUT

control input. Variations:

ENTruth Table

EN IN OUT0 X Hi-Z1 0 0

IN OUT1 0 01 1 1EN

Hoang Trang Reference: Chapter 2 - Part 3 23

. . .