COMBINATIONAL LOGIC DESIGN PRACTICES

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

DOCUMENTATION

WHAT? SPECIFICATION: INTERFACE, FUNCTION

HOW? BLOCK DIAGRAM SCHEMATIC DIAGRAM TIMING DIAGRAM STRUCTURED LOGIC DEVICE DESCRIPTION CIRCUIT DESCRIPTION

BLOCK DIAGRAMS

INPUTS, OUTPUTSFUNCTIONAL MODULESDATA PATHSCONTROL SIGNALS

BLOCK DIAGRAMS

PROCESSOR

DECODINGLOGIC

MEMORY

16

816

CS~

R/W

DATA

BUS

COLLECTION OF TWO OR MORE RELATED SIGNALS

SLASH AND NUMBER: NUMBER OF SIGNALS

SIGNAL NAMES

WELL CHOSEN NAMES CONVEY INFORMATION

SIGNAL ACTIVE LEVELS

ACTIVE HIGHACTIVE LOWASSERTED WHEN AT THE ACTIVE

LEVELDEASSERTED (NEGATED) WHEN NOT

AT THE ACTIVE LEVEL

NAMING CONVENTION

ACTIVE HIGH: GO, PAUSE, READYACTIVE LOW: GO~, PAUSE.L, /READY,

ETC.

ACTIVE LEVELS FOR PINS

INVERSION BUBBLE: ACTIVE LOWNO INVERSION BUBBLE: ACTIVE

HIGH

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

CIRCUIT TIMING

TIMING DIAGRAM RELATIONSHIPS AMONG INTERNAL SIGNALS REQUIREMENTS ON EXTERNAL SIGNALS

CAUSALITYDELAY TIMING TABLEDELAYS RANGE: MINIMUM, MAXIMUM,

TYPICALPROPAGATION DELAY (tHL, tLH,…)

TIMING SPECIFICATIONS

MAXIMUM: HOW DID THEY MEASURE IT? TEMPERATURE (25 °C, 40 °C, …) CAPACITIVE LOAD (0 pF, 50 pF, …) VCC (3.3V, 5V, …)

TYPICAL IDEAL?

MINIMUM WORK FOR ZERO DELAY? TEMPERATURE, LOAD, VCC, …

TIMING ANALYSIS

COMPLEX FOR LARGE CIRCUITSCAD TOOLS HELP, BUT:

NEED TO UNDERSTAND WHAT THE RESULTS ARE

OFTEN MANY CONTROLS NEED TO KNOW HOW TO TEST

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

DECODERS

MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS

INPUT AND OUTPUT CODES ARE DIFFERENT

ONE-TO-ONE MAPPING

DECODERS

BINARY DECODERS

n-TO-2n DECODERSACTIVATE EXACTLY ONE OF 2n

OUTPUTS BASED ON n-BIT INPUTS

2-TO-4 BINARY DECODER

LOGIC SYMBOLS

ONE-HALF OF 74x139 DECODER

ONE-HALF OF 74x139 DECODER

74x138 3-TO-8 DECODER

CASCADING BINARY DECODERS

74x138 HAS BOTH ACTIVE HIGH AND ACTIVE LOW ENABLE INPUTS

WITH TWO 138s WE CAN ENABLE OR THE OTHER USING THE MSB

SEVEN-SEGMENT DECODER

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

ENCODERS

MULTIPLE INPUT, MULTIPLE OUTPUT CIRCUIT THAT CONVERTS CODED INPUTS TO CODED OUTPUTS

OUTPUT CODE HAS FEWER BITSONE-TO-ONE MAPPING

BINARY ENCODER

2n-TO-n ENCODERINPUT: 1-OUT-OF-2n CODEOUTPUT: n-BIT BINARY CODE

BINARY ENCODER

BINARY ENCODER

Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7

PRIORITY ENCODERS

8-INPUT PRIORITY ENCODER

74x148 PRIORITY ENCODER

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

THREE-STATE DEVICES

ENABLE - DEVICE “FLOATS”FLOATS = HIGH IMPEDANCE STATE = = HI-Z STATE = DISCONNECTED

STATE

MULTIPLE SOURCES ON THREE-STATE PARTY LINE

MULTIPLE THREE-STATE DEVICES CAN SHARE SINGLE LINE

FIGHTINGDEAD TIME

MULTIPLE SOURCES ON THREE-STATE PARTY LINE

STANDARD THREE-STATE BUFFERS

HYSTERESIS?BUFFERSTRANSCEIVERS

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

MULTIPLEXERS

DIGITAL SWITCH

MULTIPLEXERS

1

0

n

jj iDjMENiY

74x151, 74x157

74x153

THREE-STATE MUXES

DISABLED OUTPUT HI-Z INSTEAD OF 0: 74x151 74x251 74x153 74x253 74x157 74x257

EXPANDING MUXES

EXPAND THE NUMBER OF BITS MULTIPLE 74x151s…

FANOUTEXPAND THE NUMBER OF SOURCES

MUXES, DEMUXES, BUSES

MUXES, DEMUXES, BUSES

DECODERS AS DEMUXES

DECODERS AS DEMUXES

DESIGN EXAMPLE

CREATE A MUX-DEMUX SYSTEM FOR A 2-BIT BUS

4 2-BIT INPUTS TO 4 2-BIT OUTPUTSUSE STANDARD TTL CHIPS FROM

BOOK

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

XOR FUNCTION

XY=X’Y + XY’

XOR MULTIGATE DESIGN

XOR MULTIGATE DESIGN

XOR GATES

ANY TWO SIGNALS MAY BE COMPLEMENTED

PARITY

COMBINATIONAL LOGIC DESIGN PRACTICES

DOCUMENTATIONTIMINGDECODERSENCODERSTHREE-STATE DEVICESMULTIPLEXERSXOR GATES AND PARITY CIRCUITSCOMPARATORS

COMPARATORS

EQUALITY - COMPARATORSARITHMETIC RELATIONSHIP -

MAGNITUDE COMPARATORS

4-BIT COMPARATOR

ITERATION?

n. THE ACTION OR A PROCESS OF REPEATING AS: A PROCEDURE IN WHICH REPETITION OF A

SEQUENCE OF OPERATIONS YIELDS A RESULT SUCCESSIVELY CLOSER TO A DESIRED RESULT

THE REPETITION OF A SEQUENCE OF COMPUTER INSTRUCTIONS A SPECIFIED NUMBER OF TIMES OR UNTIL A CONDITION IS MET

ITERATIVE CIRCUITS

ITERATIVE ALGORITHM:1. SET C0 TO INITIAL VALUE, SET i TO 0

2. USE Ci AND PIi TO TO GET POi AND Ci+1

3. INCREMENT i 4. IF i<n GO TO STEP 2

ITERATIVE COMPARATOR

74x85 COMPARATOR

ARITHMETIC CONDITIONS