8.ECE 301 - Behavioral Modeling II

7/27/2019 8.ECE 301 - Behavioral Modeling II

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VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Verilog HDL -

Prof.S.Sivanantham

VIT University

Vellore, Tamilnadu. India

E-mail: [email protected]


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After completing this lecture, you will be able to:

Understand the features of timing controls

Understand the features of selection constructs

n ers an e ea ures o oop cons ruc s

ECE301 VLSI System Design FALL 2011 S.Sivanantham


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Coding style: In the always block

Use nonblocking operators (


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Timing controls specify the simulation time at which.

In Verilog HDL, if there are no timing control statements,the simulation time will not advance.

Timing Controls

Delay timing control

Intra assignment delay control

Event timing control

ge- r ggere even con roo Named event control

o Event or control


Level-sensitive event control


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Regular delay control

A non-zero delay is specified to the left of a proceduralassignment.

.

reg x, y;n eger coun ;

// The


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-

Intra-assignment delay control

A non-zero delay is specified to the right of theassignment operator.

- - .

y = #25 ~x; // evaluate at time 0 but assign to y at time 25=

y


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Event Timing Control

An event is the change in the value on a variable or a net. The execution of a procedural statement can be

.

Two types of event control

Ed e-tri ered event control

Named event control

Event orcontrol

eve -sens t ve event contro



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-

Edge-triggered event control

The symbol @ is used to specify such event control.

@(posedge clock): at the positive edge

always @(posedge clock) beginreg


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A named event

is declared with the keywordevent.

does not hold any data.

s r ggere y e sym o ->.

is recognized by the symbol @.

event received_data; // declare an event received_data

// trigger event received_data

always @(posedge clock) if (last_byte) -> received_data;

a ways (receive _ ata) egin .. en execute event- epen ent operations



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Event orcontrol

uses the keywordorto specify multiple triggers.

can be replaced by the ,.

can use or o mean a c ange on any s gna .

alwa s osed e clock orne ative reset n // event orcontrol_

begin

if (!reset_n) q


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-

Level-sensitive event control

uses the keywordwait.

always

wait (count_enable) count = count 1 ;

always= _



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Selection structures

make a selection according to the given condition.

Two types

e se s a emen

case statement

if statement only

if and one else statement

nested if-else-if statement

The else part is always associated to the closest previous if


that lacks an else.


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if () true_statement ;

if () true_statement; else false_statement;

if () true_statement1;

else if() true_statement2;e se a se_s a emen ;



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module mux4_to_1_ifelse (i0, i1, i2, i3, s1, s0, out);

input i0, i1, i2, i3;

input s1, s0;

output reg out; s1using con itiona operator i e se statement

always @(*) // triggered for all signals used in the if else statement

if (s1)beginif s0 out = i3 else out = i2 end

un1_s1_1

ed

i3

elsebegin

if (s0) out = i1; else out = i0; end

endmodule

un1_s1_2

ed

ed

ed

out

i2i1

i0

un1_s0_1

ou


un1_s0_2


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-

module counter (clock, clear, qout);

,

output reg [3:0] qout;

// the body of the 4-bit counter.

always @(negedge clock or posedge clear)

egin

if (clear)

qout


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case statement: a multiway selection.

compares t e express on to t e a ternat ves n t e or er

they are written. com ares 0, 1, x, and z values in the ex ression and the

alternative bit for bit.

executes the default statement if no matches are made.

expression and the alternative.

is acted like a multiplexer.

The default statement is optional and at most one defaultstatement can be placed inside one case statement.

A block statement must be rou ed b be in andend.



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- -

// a 4-to-1 multiplexer using case statement

_ _ , , , , ,

input I0, I1, I2, I3;

input [1:0] S; // declare S as a two-bit selection signal.

output reg Y;

a ways (I0 or I1 or I2 or I3 or S) It can use a ways ( ).

case (S)

2'b00: Y = I0;

2'b01: Y = I1

un1_S_2

[0]

[1]S[1:0]

[1:0]

2'b10: Y = I2;

2'b11: Y = I3;

endcaseun1_S_3

ed

ed

ed

e

[0]

[1]

Y

I2I1

en mo u e

un1_S_4

Y

d

[1]

[0]

I3


Y9

[0]

[1]


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- -

// a 4-to-1 multiplexer using case and default statements.

module mux4_to_1_case_default (i0, i1, i2, i3, s1, s0, out);

input i0, i1, i2, i3, s1, s0;

output reg out; output ec are as reg ster

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0}) // concatenate s1 and s0 as a two-bit selection signals

2'b00: out = i0;

2'b01: out = i1;

2'b10: out = i2;

2'b11: out = i3;

' .

endcase

endmodule



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casex and casez statements

are used to perform a multiway selection like that of case

statement.

-

and the case alternatives.

casez treats all z values as dont cares.

casex treats all x and z values as dont cares.



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an examp e ustrat ng ow to count t e tra ng zeros n a n e.

module trailing_zero_4b (data, out);input [3:0] data;

out ut re 2:0 out //out ut declared as re ister

always @(data)

casex (data) // treat both x and z as dont care conditions.

4'bxxx1: out = 0;' xx : ou = ;

4'bx100: out = 2;

4'b1000: out = 3;

4'b0000: out = 4;

default: out = 3'b111; //using default to include all other possible cases.endcase

endmodule


8.ECE 301 - Behavioral Modeling II

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