5.ECE 301 - Structural Modeling

7/27/2019 5.ECE 301 - Structural Modeling

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VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Structural Modeling

Prof.S.Sivanantham

VIT University

Vellore, Tamilnadu. India

E-mail: [email protected]


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After completing this chapter, you will be able to:

Describe what is the structural modeling

Describe how to instantiate gate primitives

escr e ow o mo e a es gn n ga e pr m ves

Describe inertial and transport delays

Describe hazards and their effects in gate networks

ECE301 VLSI System Design FALL 2011 S.Sivanantham

Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley


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Components of Verilog Module



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Structural style: Modeled as a set of interconnected

components.

Modules/UDPs

- .

- A gate-level module is usually synthesizable.

Gate primitives: There are 12 gate primitives.

- Gate primitives are synthesizable.

Switch primitives: There are 16 switch primitives.

- They are usually used to model a new logic gatecircuit at switch level.


- , .


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and/or gates

ave one sca ar output an mu t p e sca ar nputs

are used to realize the basic logic operations

and or xor nand nor xnor

buf/not gates have one scalar input and one or multiple scalar outputs

are used to realize the not operation,

,

are used as controlled buffers

include


buf not bufif0 notif0 bufif1 notif1


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i1i2

i1i2out out

i2and i2nandx z

0

11

0 0 0 0

0 1 x x

x z

0

11

1 1 1 1

1 0 x x

x

z

i

0 x x x

0 x x x

x

z

i

1 x x x

1 x x x



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i1i2

i1i2out out

i2or i2norx z

0

11

0 1 x x

1 1 1 1

x z

0

11

1 0 x x

0 0 0 0

xz

i

x 1 x xx 1 x x

xz

i

x 0 x xx 0 x x



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i1i2

i1i2out out

i2 i20 1 x z

0

1

0 1 x x

1 0 x x

0 1 x z

0

1

1 0 x x

0 1 x x

x

z

i x x x x

x x x x

x

z

i x x x x

x x x x



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in outin out

outin 0

outin

1

1

x

1

x

1

x

0

x

z x



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in outin out

ctrlnotif0ctrlbufif0x z

0

1n

1 z H H

0 z L L

x z

0

1n

0 z L L

1 z H H

xz

i

x z x xx z x x

xz

i

x z x xx z x x


Note that: L represents 0 or z and H represents 1 or z.


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in out

ctrl

in out

ctrl

ctrlnotif1ctrlbufif1

0

1in

z 1 H H

z 0 L L

0

1in

z 0 L L

z 1 H H

xz

z x x xz x x x

xz

z x x xz x x x



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To instantiate and/or gates

instance_name is optional.

gatename [instance_name](output, input1, input2, ..., inputn);

module basic_gates (x, y, z, f) ;

input x, y, z;

x

y

bg1

wire a, b, c; // internal nets

// Structural modeling using basic gates.

nor g1 (b, x, y);

z

ac

g3not g a, x ;and g3 (c, a, z);

nor g4 (f, b, c);

endmodule



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Array instantiations may be a synthesizer dependent!

Suggestion: you had better to check this feature before

using the synthesizer.

wire [3:0] out, in1, in2;

//basic array instantiations of nand gate.

nand n_gate[3:0] (out, in1, in2);

// this is equivalent to the following:

nand n_gate0 (out[0], in1[0], in2[0]);

nand n ate1 out 1 in1 1 in2 1_

nand n_gate2 (out[2], in1[2], in2[2]);nand n_gate3 (out[3], in1[3], in2[3]);



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--- -

module full_adder_structural(x, y, c_in, s, c_out);

// I/O port declarations

input x, y, c_in;

output s, c_out;wire s1, c1, c2, c3;

- .

xor xor_s1(s1, x, y); // compute sum.

xor xor_s2(s, s1, c_in);

and and_c1(c1, x, y); // compute carry out.and and_c2(c2, x, c_in);

and and_c3(c3, y, c_in);

or or_cout(c_out, c1, c2, c3);

y

c_ins

x s1

c1

c_outc2


c3


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--- - -i0

i1

y0

y1

module mux4_to_1_structural (i0, i1, i2, i3, s1, s0, out);

input i0, i1, i2, i3, s1, s0;

out

i2

i3

y2

y3

output out;

wire s1n, s0n; // Internal wire declarations

wire y0, y1, y2, y3;// Gate instantiations s1 s0

not (s1n, s1); // Create s1n and s0n signals.

not (s0n, s0);

and (y0, i0, s1n, s0n); // 3-input and gates instantiated

an y , , s n, s ;and (y2, i2, s1, s0n);

and (y3, i3, s1, s0);

or out, 0, 1, 2, 3 ; // 4-in ut or ate instantiated


endmodule


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--- -

cx[0]x[1]

g

x[2]x[3]

x 4

d

e

i

op

x[5]

x[6]x[7]

f

h

x[8]



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--- -

module arit en 9b structural x e o_ _ _

// I/O port declarations

input [8:0] x;

output ep, op;

w re c, , e, , g, , ;

xor xor_11(c, x[0], x[1]); // first level

xor xor_12(d, x[2], x[3]);

xor xor_13(e, x[4], x[5]);

xor xor_14(f, x[6], x[7]);

xor xor_21(g, c, d); // second level

xor xor_22(h, e, f);

_ , ,

xor xor_ep(ep, i, x[8]); // fourth level

xnor xnor_op(op, i, x[8]);

endmodule



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To instantiate tristate buffers

The instance_name is optional.

buf_name[instance_name](output, input, control);

// Data selector 2-to-1 mux

module two_to_one_mux_tristate (x, y, s, f);npu x, y, s;

output f;

// internal declaration

tri f;

x

f

y

// data selector bodybufif0 b1 (f, x, s); // enable if s = 0

bufif1 b2 (f, y, s); // enable if s = 1S



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triand/wand

0

0 1 x z

0 0 0 0

trior/wor

0

0 1 x z

0 1 x 0

1

x

z

0

0

0

1

x

1

x

x

x

1

x

z

1

x

z

1

x

0

1

1

1

1

x

x

1

x

z



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module open_drain (w, x, y, z, f);

npu w, x, y, z;

output f;wand f; // internal declaration

// wired AND logic gate

VDD

nand n1 (f, w, x);

nand n2 (f, y, z);

endmodule

RL

w Q2n

y

f

Q2n

w

x

x Q1n

zQ1n y

z

f


f wx yz= ( )' ( )'


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Representing Hierarchy

Create hierarchy by n_sum

fulladd

Instantiating module(s)

Connecting module ports

to local port, net or variable

a

b

U1

halfadd

U2

halfadd n_carry2

sum

You must ec are most oca

objects before you use them

_ carry

modul e f ul l add ( i nput a, b, ci n, out put sum, carry) ;wi r e n_sum, n_carry1, n_carry2;hal f add U1( . a( a) , . b( b) , . sum( n_sum) , . carry( n_carry1) ) ;hal f add U2( . a( n sum) , . b( ci n) , . sum( sum) , . carry( n car r y2) ) ;_ _

or U3( carry, n_carry2, n_carry1) ;endmodul e

Built-in OR primitive



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Connecting Hierarchy Ordered Port Connection

Map local port, net or variable to

instance port by position in the instance

fulladd

U1

halfadd

a

b

sum

carry

n_sum

n_carry1

a

bWith this syntax you canvery easily make a

mistake!

modul e f ul l add ( i nput a, b, ci n, out put sum, carry) ;wi r e n_sum, n_carry1, n_carry2;

hal f add U1( a, b, n_sum, n_carry1) ;a a n_sum, c n, sum, n_carry ;

or U3( carry, n_carry2, n_carry1) ;endmodul e

wire n_carry1 of module

fulladdmapped to output

carry of instance U1 of

modul e hal f add ( a, b, sum, carry) ;i nput a, b;out put sum, carry;

assi gn sum = a ^ b;halfadd

a summodule


assi gn carry = a & b;endmodul e


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Inertial delay model

The signal events do not persist long enough will not be

propagated to the output.

.

It is the default delay model for HDL (Verilog HDL and

VHDL). Transport delay model

Any signal events will be propagated to the output.

It is used to model net (i.e. wires) delays. The default delay of a net is zero.



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xy

fax

42 6 8 10 12 14 16 18 20

b

b

y

42 6 8 10 12 14 16 18 20

wire a;

and #4 (b, x, y); // Inertial delay

and #4 (a, x, y);

not #1 f a

a

42 6 8 10 12 14 16 18 20

42 6 8 10 12 14 16 18 20

f

42 6 8 10 12 14 16 18 20Inertial delay



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x

y fa

x

b

y

42 6 8 10 12 14 16 18 20

wire #2 a; // Transport delay

and #4 (b, x, y); // Inertial delay

and #4 (a, x, y);a

b

42 6 8 10 12 14 16 18 20

,

f

42 6 8 10 12 14 16 18 20

Inertial delay



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Gate Delay Specifications

Specify propagation delay only:

gatename #(prop_delay) [instance_name](output, in_1, in_2,);

gatename #(t_rise, t_fall) [instance_name](output, in_1, in_2,);

Specify rise, fall, and turn-off times: gatename #(t_rise, t_fall, t_off) [instance_name](output, in_1,

in_2,);

Delay specifier: min:typ:max



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// Only specify one delayand #(5) a1 (b, x, y);

// Only specify one delay using min:typ:max

not #(10:12:15) n1 (a, x);

// Specify two delays using min:typ:max

and #(10:12:15, 12:15:20) a2 (c, a, z);

or #(10:12:15, 12:15:20, 12:13:16) o2 (f, b, c);



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A hazard is an unwanted short-width output signal when the

nputs to a com nat ona c rcu t c anges.

These unwanted signals are generated when different paths

.

Static hazard

Dynamic hazard

10 01 0 1 0 1 0 1 1 0 1 0

(b)static-0 hazard(a) static-1 hazard (c) dynamic hazard



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x

y

a

z b

c

module hazard_static (x, y, z, f);

input x, y, z;

output f;

x

y

tpdtpd


wire a, b, c; // internal net

// logic circuit body

x'

z tpd

, ,

not #5 n1 (c, x);and #5 a2 (b, c, z);

or #5 o2 (f, b, a);

a

btpd

tpd

tpd tpd tpd


endmodule fpd pd

Hazard


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x

3

b

d

z

f

1w

y

c

e

w

x =y =z = 1

a

b

d

e


fynam c azar


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// dynamic hazard example

module hazard_dynamic(w, x, y, z, f);input w, x, y, z;


wire a, b, c, d, e; // internal net

// logic circuit bodynand #5 nand1 (b, x, w);

not #5 n1 (a, w);

nand #5 nand2 (c, a, y);

nand #5 nand4 (e, w, z);nand #5 nand5 (f, d, e);

endmodule



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`timescale 1ns / 1ns

module hazard_dynamic_tb;

reg w, x, y, z; Interna signa s ec arations:

wire f;// Unit Under Test port map

hazard d namic UUT_

.w(w),.x(x),.y(y),.z(z),.f(f));

initial

beginw = ; x = ; y = ; z = ;

#5 x = 1'b1; y = 1'b1; z = 1'b1;

#30 w = 1'b1;

#20 w = 1'b0;

#190 $finish; // terminate the simulationend

initial

" "


,, , , , , ,

endmodule

5.ECE 301 - Structural Modeling

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