12.ECE 301 - Sequential Logic Modules I

7/27/2019 12.ECE 301 - Sequential Logic Modules I

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VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Verilog HDL

Prof.S.Sivanantham

VIT University

Vellore, Tamilnadu. India

E-mail: [email protected]


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After completing this lecture, you will be able to:

Describe how to model asynchronous and synchronousD-type flip-flops

, ,

and synchronous RAM)

Describe how to model shift registers

ECE301 VLSI System Design FALL 2011 S.Sivanantham


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Commonly used sequential logic modules:

ync ron zer

Finite state machine

Data register

Shift register CRC generator

Register file

, ,

Timing generator

Clock generator


Pulse generator


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Options for modeling sequential logic:

Behavioral statement

Task with delay or event control

equen a

Instantiated library register cell



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- -

Asynchronous resetD-type flip-flop

The reset signal is embodied into the event-sensitivity listof always statement.

// asynchronous reset D-type flip-flop

module DFF_async_reset (clk, reset_n, d, q);

input clk, reset_n, d;

// the body of flip flop

always @(posedge clk or negedge reset_n)

if (!reset_n) q


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- -

Synchronous resetD-type flip-flop

The reset signal is not embodied into the event-sensitivitylist of always statement.

// synchronous reset D-type flip-flop

module DFF_sync_reset (clk, reset, d, q);

input clk, reset, d;

// the body of flip flop

always @(posedge clk)

if (reset) q


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Registers (or data registers) provide a means for storing.

Types of registers used in digital systems:

Data re isterusin fli -flo s or latches.

Register filebeing used in data paths.

Synchronous RAM (random access memory) being used.

A flip-flop may take up 10 to 20 times the area of a 6-transistor static RAM cell.

In Xilinx FPGA, both register file and synchronous RAMare synthesized into static RAM structures consisting ofLUTs or block RAMs.



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din[3] din[2] din[1] din[0]

D

CK

Q

Q'

D

CK

Q

Q'

D

CK

Q

Q'

D

CK

Q

Q'

clk

qout[0]qout[3] qout[2] qout[1]

-

module register(clk, din, qout);

parameter N = 4; // number of bits

input clk;

input [N-1:0] din;output reg [N-1:0] qout;

// the body of an n-bit data register

=


endmodule


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// an n-bit data register with asynchronous reset

_ , _ , ,

parameter N = 4; // number of bitsinput clk, reset_n;

input [N-1:0] din;

output reg [N-1:0] qout;

// The body of an n-bit data registeralwa s osed e clk or ne ed e reset n_

if (!reset_n) qout


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// an N-bit data register with synchronous load and

module register_load_reset (clk, load, reset_n, din, qout);parameter N = 4; // number of bits

input clk, load, reset_n;

input [N-1:0] in;


// the bod of an N-bit data re ister


if (!reset_n) qout


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// an N-word register file with one-write and two-read ports

_ , _ , _ , _ , _ , , ,

parameter M = 4; // number of address bitsparameter N = 16; // number of words, N = 2**M

parameter W = 8; // number of bits in a word

input c , wr_ena e;

input [W-1:0] din;

output [W-1:0] douta, doutb;in ut M-1:0 rd addra rd addrb wr addr _ _ _

reg [W-1:0] reg_file [N-1:0];

// the body of the N-word register file

ass gn ou a = reg_ e r _a ra ,doutb = reg_file[rd_addrb];

always @(posedge clk)

if (wr_enable) reg_file[wr_addr]


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// a synchronous RAM module example

module syn_ram (addr, cs, din, clk, wr, dout);

parameter N = 16; // number of wordsparameter A = 4; // number of address bits

=

input [A-1:0] addr;

input [W-1:0] din;

input cs, wr, clk; // chip select, read-write control, and clock signalsoutput reg - : out;

reg [W-1:0] ram [N-1:0]; // declare an N * W memory array

// the bod of s nchronous RAM

always @(posedge clk)if (cs) if (wr) ram[addr]


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Shift registers perform left or right shift operation.

Parallel/serial format conversion:

SISO (serial in serial out)

ser a n para e ou

PISO (parallel in serial out)



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D

CK

Q D

CK

Q D

CK

Q D

CK

Q

QD

QC

QB

QA

Serial input(SI)

Serial output(SO)

CP

CP

Q' Q' Q' Q'

QA

SI

1 1 0 1

B

QC

QD

0 0 0 1 1 0 1

0 0 1 1 0 1



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// a shift register module example

module shift_register(clk, reset_n, din, qout);Parameter N = 4; // number of bits

, _

input din;


// the body of an N-bit shift register


if (!reset_n) qout


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// a shift register with parallel load module example

module shift_register_parallel_load(clk, load, reset_n, din, sin, qout);parameter N = 8; // number of bits

, , , _

input [N-1:0] din;


// the body of an N-bit shift register


if (!reset_n) qout


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A universal shift register can carry out

SISO (serial in serial out)

SIPO (serial in parallel out)

para e n ser a ou

PIPO (parallel in parallel out)

Parallel load

Serial in and serial out

Shift left and shift right



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Right

shift serial

input

Left shift

serial

input

din[3] din[2] din[1] din[0]

D QD QD QD Q

s0s1 4-to-1

MUX

0123

Y

0123

Y

0123

Y

0123

Y

clk

CKQ'

clear

CKQ'

clear

CKQ'

clear

CKQ'

clear

reset

Paralle data input

Right shift

serial input

Left shift

serial inputs1 s0 Function

qou qou qou qou

D C B ACLRreset

clkQD

QC

QB

QA

CK

S1

S0

Mode

control

4-bit universal

shift register0 1

1 0

Right shift

Left shift


Paralle data output


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// a universal shift register module

module universal_shift_register (clk, reset_n, s1, s0, lsi, rsi, din, qout);

parameter N = 4; // define the size of the universal shift registerinput s1, s0, lsi, rsi, clk, reset_n;

-


// the shift register body

always @(posedge clk or negedge reset_n)reset_n qout

12.ECE 301 - Sequential Logic Modules I

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