ECE 301 – Digital Electronics Sequential Logic Circuits: State Assignment And State Minimization...

ECE 301 – Digital Electronics

Sequential Logic Circuits:

State AssignmentAnd

State Minimization

(Lecture #20)

ECE 301 - Digital Electronics 2

State Assignment Problem


State Assignment Problem Some state assignments are better than others. The state assignment influences the complexity of the

state machine. The combinational logic required in the state machine

design is dependent on the state assignment.

Types of state assignment Binary encoding: 2N states → N Flip-Flops Gray-code encoding: 2N states → N Flip-Flops One-hot encoding: N states → N Flip-Flops


Example:

Design a FSM that detects a sequence of two or more consecutive ones on an input bit stream.

The FSM should output a 1 when the sequence is detected, and a 0 otherwise.

This is another example of a sequence detector.

FSM: State Assignment



Input: 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 …

Output: 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 …



State Diagram

C z = 1

Reset

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

S0 / 0 S1 / 0

S2 / 1



State Table

Present State Next State Output

w = 0 w = 1

S0

S0

S1

0

S1

S0

S2

0

S2

S0

S2

1


FSM: State Assignment #1

State Assigned Table


w = 0 w = 1

QA

QB

QA

+ QB

+ QA

+ QB

+ z

S0

0 0 S0

0 0 S1

0 1 0

S1

0 1 S0

0 0 S2

1 0 0

S2

1 0 S0

0 0 S2

1 0 1

1 1 d d d d d

Using Binary Encodingfor the State Assignment



Present State Next State FF Inputs

w = 0 w = 1 w = 0 w = 1

QA

QB

QA

+ QB

+ QA

+ QB

+ DA

DB

DA

DB

S0

0 0 0 0 0 1 0 0 0 1

S1

0 1 0 0 1 0 0 0 1 0

S2

1 0 0 0 1 0 0 0 1 0

1 1 d d d d d d d d


Characteristic Equation: D = Q+



K-Map and Boolean expression for z



D Q

Q

D Q

Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

A

Bw

zDA = w.(Q

A + Q

B)

DB = w.Q

A'.Q

B'

z = QA





w = 0 w = 1

QA

QB

QA

+ QB

+ QA

+ QB

+ z

S0

0 0 S0

0 0 S1

0 1 0

S1

0 1 S0

0 0 S2

1 1 0

S2

1 1 S0

0 0 S2

1 1 1

1 0 d d d d d

Using Gray-code Encodingfor the State Assignment



Present State Next State FF Inputs

w = 0 w = 1 w = 0 w = 1

QA

QB

QA

+ QB

+ QA

+ QB

+ DA

DB

DA

DB

S0

0 0 0 0 0 1 0 0 0 1

S1

0 1 0 0 1 1 0 0 1 1

S2

1 1 0 0 1 1 0 0 1 1

1 0 d d d d d d d d





K-Map and Boolean expression for DA, D

B and z



D Q

Q

D Q

Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

A

B

DA = w.Q

B

DB = w

z

z = QA




Present State Next State

w = 0 w = 1

QA

QB Q

CQ

A+ Q

B+ Q

C+ Q

A+ Q

B+ Q

C+

S0

0 0 1 S0

0 0 1 S1

0 1 0

S1

0 1 0 S0

0 0 1 S2

1 0 0

S2

1 0 0 S0

0 0 1 S2

1 0 0

Using One-hot Encodingfor the State Assignment

For each state only one flip-flop is set to 1.The remaining combination of state variables are not used.




Resetn

D Q

Q

D Q

Q Clock

D Q

Q

DA = w.Q

C' z

z = QA

A

B

C

DB = w.Q

C

DC = w.' w


State Minimization


Definition:

Two states Si and Sj are said to be equivalent if and only if for every possible input sequence, the same output sequence will be

produced regardless of whether Si or Sj is the initial state.

FSM: State Minimization


Definition:

A partition consists of one or more blocks, where each block comprises a subset of states that may be equivalent, but the states in

a given block are definitely not equivalent to the states in other blocks.



State Minimization: Partitioning State Minimization through Partitioning:

– Form an initial partition (P1) that includes all states.

– Form a second partition (P2) by separating the states

into two blocks based upon their output values.

– Form a third partition (P3) by separating the states into

blocks corresponding to the next state values.

– Continue partitioning until two successive partitions are the same (i.e. P

N-1 = P

N).

– All states in any one block are equivalent. Equivalent states can be combined into a single state.


Example:

Use partitioning to minimize the number of states in the following Finite State Machine (FSM).

State Minimization: Partitioning



State Diagram

G / 0 F / 0

E / 0D / 1

B / 1 C / 0

A / 1



Present Next state Outputstate w = 0 w = 1 z

A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0



Initial Partition:

P1 = (ABCDEFG)

The initial partition contains all states in the state diagram / table.




A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0

Separate states based on output value. P

2 = (ABD)(CEFG)



Separate states based on next state values.

P3 = (ABD)(CEG)(F)

ABD CEFG

BDB CFG FFEF ECDG

0 1 0 1

unique state




P4 = (AD)(CEG)(F)(B)

ABD CEG

BDB CFG FFF ECG

0 1 0 1

unique states




P5 = (AD)(CEG)(F)(B)

AD CEG

BB CG FFF ECG

0 1 0 1

same as previous partition (P4)


State Minimization: Partitioning Since P

4 = P

5, state minimization is complete.

The equivalent states are: A = D C = E = G B F

Thus, the FSM can be realized with just 4 states.




A B C 1 B A F 1 C F C 0 F C A 0

Minimized State Table



Minimized State Diagram


Acknowledgments

The slides used in this lecture were taken, with permission, from those provided by McGraw-Hill for

Fundamentals of Digital Logic with VHDL Design (3rd Edition).

They are the property of and are copyrighted by McGraw-Hill Higher Education.

ECE 301 – Digital Electronics Sequential Logic Circuits: State Assignment And State Minimization...

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